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UVM RAL Verification Labs
Lab 5of 25

  1. RAL Foundations and Register Modeling5

  2. Register Access and State Synchronization5

  3. Register Access Policies and Hardware Side Effects5

  4. Advanced Register Architecture and Verification5

  5. Expert RAL Debugging and Integrated IP Verification5

Lab 05RAL Foundations and Register ModelingPublished

Frontdoor Register Access

Beginner~75 min

Problem statement

How do you connect a register model to an APB sequencer and verify frontdoor register reads and writes against RTL?

Learning objective

Attach the register model's map to the APB sequencer through the adapter and verify that frontdoor write() and read() calls reach and return the RTL register contents.

Prerequisite concepts

  • The APB register adapter (Lab 04)
  • Register block and address map (Lab 03)
  • Running a sequence on a sequencer

Concepts covered

  • set_sequencer()
  • Frontdoor
  • write()
  • read()
  • uvm_status_e
This lab is part of UVM RAL Verification Labs

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