All UVM RAL labs
UVM RAL Verification Labs
Lab 11of 25
RAL Foundations and Register Modeling5
Register Access and State Synchronization5
Register Access Policies and Hardware Side Effects5
Advanced Register Architecture and Verification5
Expert RAL Debugging and Integrated IP Verification5
Lab 11Register Access Policies and Hardware Side EffectsPublished
RO, RW, and WO Register Verification
Intermediate~75 min
Problem statement
How do you verify RO, RW, and WO register fields, including illegal writes and readback behavior?
Learning objective
Verify that read-only, read-write and write-only fields respond correctly to legal and illegal accesses, and that the model predicts each response.
Prerequisite concepts
- Register field modeling (Lab 02)
- Explicit register prediction (Lab 09)
Concepts covered
- RO
- RW
- WO
- Illegal write
- Readback
This lab is part of UVM RAL Verification Labs
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