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UVM RAL Verification Labs
Lab 17of 25

  1. RAL Foundations and Register Modeling5

  2. Register Access and State Synchronization5

  3. Register Access Policies and Hardware Side Effects5

  4. Advanced Register Architecture and Verification5

  5. Expert RAL Debugging and Integrated IP Verification5

Lab 17Advanced Register Architecture and VerificationPublished

Multiple Register Maps and Address Aliases

Advanced~105 min

Problem statement

How do you model multiple register maps for the same register storage and verify address aliases through different access paths?

Learning objective

Place the same registers in two address maps, drive each map through its own path, and verify that both views reach — and predict — the same storage.

Prerequisite concepts

  • Register arrays and address decoding (Lab 16)
  • Explicit register prediction (Lab 09)

Concepts covered

  • Multiple maps
  • Address aliases
  • Per-map predictor
  • Map selection
This lab is part of UVM RAL Verification Labs

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