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UVM RAL Verification Labs
Lab 18of 25

  1. RAL Foundations and Register Modeling5

  2. Register Access and State Synchronization5

  3. Register Access Policies and Hardware Side Effects5

  4. Advanced Register Architecture and Verification5

  5. Expert RAL Debugging and Integrated IP Verification5

Lab 18Advanced Register Architecture and VerificationPublished

UVM Memory Abstraction

Advanced~90 min

Problem statement

How do you implement a memory-mapped RTL RAM window using uvm_mem and verify reads, writes, and address boundaries?

Learning objective

Map an RTL RAM window into the register block as a uvm_mem and verify word access, first and last addresses, and behaviour just outside the window.

Prerequisite concepts

  • Register block and address map (Lab 03)
  • Single-port synchronous RAM in RTL

Concepts covered

  • uvm_mem
  • add_mem()
  • Memory window
  • Address boundaries
This lab is part of UVM RAL Verification Labs

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