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UVM RAL Verification Labs
Lab 24of 25

  1. RAL Foundations and Register Modeling5

  2. Register Access and State Synchronization5

  3. Register Access Policies and Hardware Side Effects5

  4. Advanced Register Architecture and Verification5

  5. Expert RAL Debugging and Integrated IP Verification5

Lab 24Expert RAL Debugging and Integrated IP VerificationPublished

Concurrent Hardware and Software Register Access

Advanced~120 min

Problem statement

How do you verify concurrent hardware updates and software register accesses while accounting for transaction ordering and side-effect races?

Learning objective

Verify registers that hardware and software touch in the same window, deciding which value is correct for each ordering and checking it without false failures.

Prerequisite concepts

  • Hardware-updated status registers (Lab 14)
  • Read-clear and write-one-to-clear fields (Labs 12–13)

Concepts covered

  • Hardware/software race
  • Transaction ordering
  • Volatile checking
  • Side-effect races
This lab is part of UVM RAL Verification Labs

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