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UVM RAL Verification Labs
Lab 22of 25

  1. RAL Foundations and Register Modeling5

  2. Register Access and State Synchronization5

  3. Register Access Policies and Hardware Side Effects5

  4. Advanced Register Architecture and Verification5

  5. Expert RAL Debugging and Integrated IP Verification5

Lab 22Expert RAL Debugging and Integrated IP VerificationPublished

Banked Register Architecture

Advanced~120 min

Problem statement

How do you verify a banked register architecture in which a selector register changes the physical storage accessed at a shared address?

Learning objective

Model a banked register whose storage depends on a selector, and keep prediction correct when the selector changes between accesses.

Prerequisite concepts

  • Multiple maps and address aliases (Lab 17)
  • Explicit register prediction (Lab 09)

Concepts covered

  • Banked registers
  • Selector register
  • Shared address
  • Bank-aware prediction
This lab is part of UVM RAL Verification Labs

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