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UVM RAL Verification Labs
Lab 20of 25

  1. RAL Foundations and Register Modeling5

  2. Register Access and State Synchronization5

  3. Register Access Policies and Hardware Side Effects5

  4. Advanced Register Architecture and Verification5

  5. Expert RAL Debugging and Integrated IP Verification5

Lab 20Advanced Register Architecture and VerificationPublished

Standard RAL Verification Sequences

Advanced~105 min

Problem statement

How do you use standard RAL register sequences to test reset, bit-bash, and access behavior, including correct exclusions for volatile and side-effect registers?

Learning objective

Run the built-in hardware-reset, bit-bash and memory-walk sequences on the register block and exclude exactly the registers whose behaviour those sequences cannot check.

Prerequisite concepts

  • Access policies and side effects (Module 3)
  • UVM memory abstraction (Lab 18)

Concepts covered

  • uvm_reg_hw_reset_seq
  • uvm_reg_bit_bash_seq
  • uvm_mem_walk_seq
  • NO_REG_TESTS
This lab is part of UVM RAL Verification Labs

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