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UVM RAL Verification Labs
Lab 7of 25

  1. RAL Foundations and Register Modeling5

  2. Register Access and State Synchronization5

  3. Register Access Policies and Hardware Side Effects5

  4. Advanced Register Architecture and Verification5

  5. Expert RAL Debugging and Integrated IP Verification5

Lab 07Register Access and State SynchronizationPublished

Backdoor Register Access

Intermediate~75 min

Problem statement

How do you implement HDL backdoor paths and verify register peek() and poke() behavior without generating bus transactions?

Learning objective

Configure HDL paths in the register model, install a user-defined backdoor, and prove that peek() and poke() read and write RTL storage directly, with no APB transfer on the bus.

Prerequisite concepts

  • RTL hierarchy and hierarchical paths
  • Desired and mirrored values (Lab 06)

Concepts covered

  • add_hdl_path()
  • add_hdl_path_slice()
  • peek()
  • poke()
  • Backdoor
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