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UVM RAL Verification Labs
Lab 13of 25

  1. RAL Foundations and Register Modeling5

  2. Register Access and State Synchronization5

  3. Register Access Policies and Hardware Side Effects5

  4. Advanced Register Architecture and Verification5

  5. Expert RAL Debugging and Integrated IP Verification5

Lab 13Register Access Policies and Hardware Side EffectsPublished

Read-Clear and Read-Set Registers

Intermediate~75 min

Problem statement

How do you verify read-clear and read-set register fields and ensure their RAL predictions reflect the RTL side effects?

Learning objective

Verify RC and RS fields, show that a read changes the stored value, and keep the mirror correct after reads issued by both the model and other bus masters.

Prerequisite concepts

  • Write-one and write-zero policies (Lab 12)
  • Explicit register prediction (Lab 09)

Concepts covered

  • RC
  • RS
  • Read side effect
  • Prediction after read
This lab is part of UVM RAL Verification Labs

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