Why Receiving Is Harder Than Transmitting

Module 4 ended with a budget and one unresolved term. δ_sample appeared in every calculation as a symbol with no value, because it belongs to a decision that module deliberately did not make: how a receiver decides when to sample.

This module makes it. And it starts by being precise about why the question is hard at all, because the usual explanation — "the receiver has no clock" — is both wrong (Chapter 1.2 settled that) and unhelpful.

The real asymmetry is about authorship. A transmitter executes a schedule it wrote itself: it decides when the frame starts, holds each interval for a duration it chose, and is finished. Nothing it does requires a judgement about the outside world. A receiver must reconstruct that schedule from evidence, and the evidence is one edge on an input whose timing it does not control.

That reconstruction turns out to require four separate decisions, none of which the transmitter faces. Enumerating them is this chapter, and each of the four becomes a later chapter of this module.

1. The Asymmetry, Stated Precisely

Put the two halves side by side and the difference is not in what they do but in who decided it.

Every entry in the right-hand column is a judgement under uncertainty. Every entry in the left is a scheduled action.

That is why a transmitter is, as Chapter 1.1 put it, mostly a matter of care: sequence the fields, hold each for the configured duration, drive the line. A defect in a transmitter is a coding error. A defect in a receiver is often a modelling error — a wrong assumption about what the evidence supports.

2. Four Decisions

Reconstruction decomposes into four questions, in order. They are separable, they are answered by different mechanisms, and each has its own failure mode.

One — is something happening? The line has been at its idle level for an unbounded time (Chapter 3.1). At some instant it departs. Detecting that departure is the detection problem, and it is complicated by the fact that the input is asynchronous to the receiver's clock — §3.

Two — was it real? Not every departure from idle is a frame. A disturbance on the conductor produces the same observation as the beginning of a transmission, and a receiver that acts on every edge will construct a frame nobody sent. Separating the two is the qualification problem, and it is Chapter 5.2.

Three — where are the positions? Having accepted a start, the receiver must place a sampling instant inside each subsequent interval. Chapter 2.2 gave the geometry — centres at (k + 0.5) x T_bit — but the receiver can only act on its own clock edges, so it needs a mechanism with enough resolution to land near those centres. That is the scheduling problem, and it is Chapter 5.3.

Four — what value was there? At the scheduled instant the receiver reads the line. One reading is a decision from one observation; some receivers take several and combine them. That is the decision problem, and it is Chapter 5.4.

The transmitter makes none of these four decisions. It has a fifth kind of task entirely — executing a schedule — and that is the whole of the asymmetry.

3. The Input Is Asynchronous, and That Is Immediate

Before any of the four decisions can be made safely, one fact has to be dealt with.

rx_i changes at instants determined by the far end's clock, which has no relationship to the receiver's (Chapter 1.2). A flip-flop sampling it can therefore have its setup or hold requirement violated, and when that happens its output may be neither a clean 0 nor a clean 1 for some interval — it may be metastable.

Two consequences matter here, and both are immediate rather than theoretical.

Feeding raw rx_i to more than one place is a correctness bug, not a style issue. If two flip-flops sample the same asynchronous transition in the same cycle, they can resolve to different values. Logic downstream then sees a state that is inconsistent rather than merely late — a state machine and a counter disagreeing about whether a start occurred, for example.

The standard answer is a synchronisation boundary, and every later chapter in this module assumes one is present.

// Synthesizable SystemVerilog — the input boundary. Two stages.
// Module 12 owns the analysis: how many stages, what MTBF that buys, how
// it is constrained, and what reset domain it belongs to. What is shown
// here is the boundary every later chapter of this module assumes.
logic rx_meta_q;    // may be metastable when it samples a transition
logic rx_sync_q;    // what the rest of the receiver uses

always_ff @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        // Reset to the IDLE level, not to zero. A receiver coming out of
        // reset must not appear to be mid-start-bit; resetting these to 0
        // presents a fabricated departure from idle to the detector.
        rx_meta_q <= 1'b1;
        rx_sync_q <= 1'b1;
    end else begin
        rx_meta_q <= rx_i;
        rx_sync_q <= rx_meta_q;
    end
end

What the first stage does is absorb the timing violation. It is the flip-flop that may go metastable, and nothing downstream reads it directly.

What the second stage provides is time — one clock period for the first stage to settle before its value is captured and used. That is the entire mechanism.

What it does not do is eliminate metastability. The probability of an unresolved event is reduced, not removed, and it cannot be made zero by adding stages. It also cannot be observed in simulation: an RTL simulator propagates a clean value, so a design with no synchroniser at all simulates perfectly and fails in hardware at a rate nobody predicted. Module 12 treats the quantification properly.

What it costs is latency and uncertainty. The transition is observed one to two clock periods after it physically occurred, and which of those it is depends on where the transition fell relative to the clock edge. The first part is a fixed delay; the second is the origin uncertainty Chapter 2.5 already put in the budget and Chapter 4.5 computed as δ_origin.

4. What Framing Requires, and What Receivers Choose

This distinction runs through the whole module and is the reason the curriculum keeps insisting on it.

UART framing places exactly one obligation on a receiver: recover the payload bits from the intervals the transmitter drove. It says nothing about how.

Everything else — how the departure from idle is detected, whether it is qualified and for how long, how many observations per bit interval, where they are placed, whether several are combined — is implementation. Different UART IPs answer these differently, all of them conforming.

5. What This Means for Verification

The asymmetry has a direct consequence for how a receiver is stimulated, and it is the single most common way a UART testbench lies.

The transmitter's timing is the testbench's to choose, and choosing it conveniently is a trap. A stimulus that drives rx_i from the same clock that runs the DUT — or that changes it exactly on a clock edge — has quietly removed the uncertainty of §3. The receiver always observes the transition at the same phase, δ_origin is always at the same value, and the design's real margin is never exercised.

The fix is to randomise the phase of every start edge across the clock period, continuously rather than at a handful of points:

// Testbench SystemVerilog — NOT synthesizable. `realtime` and absolute
// delays exist only in simulation.
//
// Drives a start edge at a deliberately arbitrary offset within the
// receiver's clock period, so the design is exercised across the whole
// range of observation phases rather than at one convenient value.
task automatic drive_start_with_phase(input realtime phase_offset);
    #(phase_offset);
    rx_i <= 1'b0;
endtask

// Usage: phase drawn across one clock period, not a fixed fraction of it.
initial begin
    realtime clk_period = 10ns;          // 100 MHz
    repeat (N_FRAMES) begin
        drive_start_with_phase($urandom_range(0, 999) * clk_period / 1000);
        // ... drive the remaining intervals at the transmitter's rate ...
    end
end

Why continuous rather than a few phases. The failure this finds is a design whose margin is adequate at some observation phases and not others. Testing four evenly spaced phases can miss a narrow bad region; drawing from a fine grid across many frames covers it statistically. The cost is nothing — it is the same test, run with a different offset.

Three further consequences of the four-decision structure, developed in their own chapters:

• Each decision needs its own negative test. A detection test does not exercise qualification, and a qualification test does not exercise scheduling. Stimulus that only sends well-formed frames tests decision four and nothing else.
• A disturbance is legitimate stimulus, not an error case. The receiver's behaviour when a glitch arrives is specified behaviour — Chapter 5.2 and Chapter 5.4 define what should happen.
• Frequency error is the normal condition. Chapter 4.5 established this; Chapter 5.5 makes it concrete at the sample positions.

6. What This Means on an FPGA

rx_i is a board pin, and it is genuinely asynchronous. Whatever is at the other end — a USB-to-serial bridge, an MCU, another FPGA — runs from its own oscillator. The synchroniser of §3 is not optional and its placement matters: it belongs immediately at the input boundary, before any fan-out, so that every consumer sees the same sampled value.

The synchroniser's reset value is a real decision. Resetting to the idle level means a receiver released from reset onto a quiet line sees idle, as it should. Resetting to zero presents a fabricated departure from idle to the detector, and the receiver begins constructing a frame that was never sent — a self-inflicted version of Chapter 3.1's stuck-at-space failure.

Everything downstream stays in one clock domain. The four decisions are made by logic clocked by clk, qualified by enables. No part of this module generates a second clock, and Chapter 5.3 gives the reason when the oversample tick is introduced.

An unconnected rx_i is the most common bring-up fault in this territory. A floating input drifts across the threshold and produces transitions that look like departures from idle. Whether the pin has a defined level when nothing is attached is a board decision, and it determines whether a disconnected cable produces silence or a flood of malformed frames.

7. Understanding Check

8. Summary

The receive side is harder because of authorship, not because of any missing clock. A transmitter executes a schedule it wrote itself and faces no judgement about the outside world. A receiver reconstructs someone else's schedule from one edge on an input it does not control.

Reconstruction decomposes into four decisions, each with its own mechanism, its own failure mode, and its own chapter: detect the departure from idle; qualify it as a genuine start rather than a disturbance; schedule a sampling instant inside each following interval; decide what value was present. The transmitter makes none of them.

Before any of the four, the input must cross a synchronisation boundary. rx_i is asynchronous, so a flip-flop sampling it can go metastable, and two flip-flops sampling the same transition can resolve differently — which is a correctness bug rather than a style issue. Two stages reduce the probability of an unresolved event; they do not eliminate it, cannot be made to, and cannot be observed in simulation. The boundary costs a fixed latency plus the observation-phase uncertainty that Chapter 4.5 budgets as δ_origin.

Framing places one obligation on a receiver — recover the payload bits — and is silent on how. Detection, qualification, sampling resolution and value decision are all implementation, which is why "UART uses 16× oversampling", "UART receivers use majority voting" and "UART tolerates 5%" are each a description of a common choice presented as a protocol requirement.

For verification the immediate consequence is that a testbench driving rx_i from the DUT's own clock has removed the observation-phase uncertainty and will not find a design whose margin depends on it.

9. What Comes Next

The first two decisions are inseparable in practice and are taken together. Chapter 5.2 builds the detector that observes a departure from idle on the synchronised input, then confronts the question that makes it interesting: a falling edge is evidence, not proof. A disturbance produces the identical observation, and a receiver that commits on every edge constructs frames nobody sent — while one that waits for confirmation spends timing budget and shifts its own reference. That trade is the chapter.

Browse the full path on the UART tutorials index. For the transmit side's contrasting simplicity — a schedule with no judgements in it — see Chapter 2.3, which first drew this asymmetry as a timing problem.