Start-Bit Synchronisation and Per-Frame Timing Recovery

Chapter 2.2 built the bit grid — boundaries at k x T_bit, centres at (k + 0.5) x T_bit — and anchored it at an origin it simply declared. "Take that instant as t = 0." Which instant, and how does the receiver know?

That is the whole of this chapter, and it is a narrower problem than it first appears. Chapter 2.1 separated the receiver's two unknowns: rate, which it is told in advance, and phase, which it is told nothing about. The grid needs both. The rate fixes the spacing of the positions; only the phase fixes where the first one is. So the receiver arrives at each frame holding exactly half the information it needs, and the missing half has to come from the signal itself.

It comes from one transition. Not a continuously recovered clock, not a training pattern, not a preamble — a single edge, once per frame, discarded and re-acquired at the next one.

1. What the Receiver Has, and What It Is Missing

State the position precisely at the moment before a frame arrives.

It has the rate. Both endpoints were configured, so the receiver knows T_bit — or rather, it knows its own approximation of it, built from whole cycles of its own clock as Chapter 2.2 §6 showed.

It has no phase whatsoever. Nothing has told it when a frame might begin, and nothing can: the transmitter sends when it has something to send. The line has been idle for an unknown and unbounded time (Chapter 1.3).

It has its own clock, free-running. Not aligned to anything, and in particular not aligned to whatever the transmitter is about to do.

A grid needs an origin and a spacing. The receiver holds the spacing and is missing the origin — which is a useful way to see how small the remaining problem is. It does not need to know the transmitter's frequency, track it, or correct for it. It needs one instant.

2. The One Transition That Is Guaranteed

Chapter 2.2 §3 established something that constrains the solution sharply: transitions inside a frame are not guaranteed. Consecutive intervals carrying the same value produce no edge at all, so a frame may contain long stretches in which the conductor does not move. A receiver cannot key off "the next transition" in general, because there may not be one for many intervals.

One transition is different. The line rests at the idle level between frames, and a frame begins by departing it. That departure is guaranteed by the framing itself — it is what makes the start of a frame detectable at all, and Chapter 1.3 showed the resting level and the opening level must differ for exactly this reason.

So the receiver's entire phase information is that one edge. Everything else about the frame's timing is inferred from it, which is why this single event carries so much weight and why the chapters after this one are largely about what happens as that inference ages.

3. From Event to Grid

The mechanism is three steps, and none of them involves the transmitter after the first.

Take the observed instant as the origin. The receiver records the moment it observed the departure from idle. Call it t = 0. This is a local record — a counter cleared, a state entered — and nothing about it is communicated anywhere.

Predict the positions. Having an origin and a spacing, the receiver computes where the intervals of this frame should fall, using Chapter 2.2's geometry: interval k centred at (k + 0.5) x T_bit from the origin. In hardware this is counting, not arithmetic — the receiver counts its own clock cycles to each predicted position in turn.

Run out the frame, then discard it. The predictions are used for N_frame intervals. Then the frame is over, the receiver returns to watching for the next departure from idle, and the origin it recorded is worth nothing.

The asymmetry in the figure is the point. One interval is observed. Nine are predicted. The receiver spends most of every frame acting on a computation rather than on evidence, and the quality of that computation is the quality of the link.

4. Per-Frame, Not Continuous

This is the distinction that separates asynchronous serial from the interfaces Chapter 1.6 grouped as embedded-clock, and getting it wrong leads to expecting behaviour the link does not have.

A continuous recovery scheme extracts timing from the data stream throughout transmission. Because transitions keep arriving, the receiver keeps refining its estimate, and a slow frequency difference is tracked out rather than accumulating. That is what a clock-recovery loop does, and it is why such links can run indefinitely without re-acquiring.

A per-frame scheme acquires once and then runs open-loop for the whole frame. There is no refinement, no feedback, no correction. The estimate can only get worse from the instant it is made — and it does, at a rate this chapter has not yet quantified.

The self-loop is where the receiver spends almost all of every frame, and the return to Idle is the mechanism Chapter 2.1 identified as load-bearing. Discarding the origin is not housekeeping — it is the thing that bounds the damage.

5. What Is Synchronised, and What Is Not

The word synchronisation appears in this chapter's title and in every description of the mechanism, and it is routinely over-read. Be exact.

Not synchronised: the two clocks. Neither oscillator is adjusted, influenced, disciplined or measured. The transmitter's crystal runs at whatever it runs at; the receiver's does the same. They were independent before the frame and are equally independent after it. Nothing in an asynchronous serial link ever changes a frequency.

Not synchronised: anything persisting between frames. The receiver does not build up a better estimate over time. Frame one teaches it nothing usable in frame two, because the origin is discarded and the next one is acquired from scratch.

What is aligned: the receiver's estimate of the transmitted grid, for this frame only. That is the entire content of the operation. The receiver's guess about where the transmitter's intervals currently lie is refreshed, and the refreshed guess is used for N_frame intervals and thrown away.

6. The Shape This Takes in Hardware

The three steps of §3 have a direct RTL form, and it is worth seeing the skeleton even though Module 6 builds the real thing.

// Synthesizable SystemVerilog — timing skeleton only. NOT a UART receiver.
//
// Deliberately absent, each with an owning chapter:
//   · qualification of frame_start_i      -> Chapter 5.2
//   · generation of bit_tick_i            -> Modules 4 and 8
//   · sampling, shifting, status, errors  -> Module 6
//   · synchronisation of the raw rx pin   -> Module 12
//
// What it shows is only this chapter's mechanism: an origin is recorded by
// clearing a counter, and every later position is counted locally from it.
module uart_phase_counter #(
    parameter int unsigned N_FRAME = 10,              // interval count, a
                                                      // parameter (Ch 2.2 §4)
    parameter int unsigned IDX_W   = $clog2(N_FRAME)
) (
    input  logic             clk,          // receiver's own clock — the only
                                           // timebase available (Ch 2.1 §5)
    input  logic             rst_n,
    input  logic             frame_start_i, // 1 cycle, at the observed edge
    input  logic             bit_tick_i,    // 1 cycle, once per bit interval
    output logic [IDX_W-1:0] bit_index_o,   // which predicted position we are on
    output logic             active_o       // inside a frame
);
    always_ff @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            bit_index_o <= '0;
            active_o    <= 1'b0;
        end else if (frame_start_i) begin
            // THE ORIGIN. Everything this chapter describes is this line:
            // the count is cleared at the observed edge, and every predicted
            // position afterwards is measured from here.
            bit_index_o <= '0;
            active_o    <= 1'b1;
        end else if (active_o && bit_tick_i) begin
            if (bit_index_o == IDX_W'(N_FRAME - 1)) begin
                active_o    <= 1'b0;   // frame complete — discard the origin
            end else begin
                bit_index_o <= bit_index_o + 1'b1;
            end
        end
    end
endmodule

Read it as the state machine of Figure 2 with the counting made explicit.

What state it holds. Two things: how far into the frame we are (bit_index_o) and whether we are in one at all (active_o). Nothing else. In particular it holds nothing about the transmitter — no measured frequency, no phase error, no history from previous frames. That absence is the architecture, not an omission.

Why it updates when it does. frame_start_i clears the count unconditionally: a new origin overrides whatever was in progress. bit_tick_i advances it one position, and arrives once per bit interval from the rate logic Module 8 builds. The two are separate inputs because they answer different questions — where is the origin and how far have we counted from it.

The timing assumption it encodes. That bit_tick_i arrives at the predicted positions. Everything about whether that is true — the construction error from Chapter 2.2 §6, the oscillator mismatch of Chapter 2.4 — lives outside this module. It counts ticks faithfully and has no way to know if they are in the right place.

Reset behaviour. Both outputs reset inactive. A receiver coming out of reset is not mid-frame, and asserting active_o from reset would make it begin predicting positions for a frame that was never started.

Width safety. IDX_W is derived with $clog2(N_FRAME) rather than hand-written, and the comparison constant is cast to that width. A hand-chosen width that is one bit short wraps the index early and silently terminates frames at the wrong interval — a defect that looks like a framing problem and is arithmetic.

7. What This Means for Verification

Per-frame acquisition creates test conditions that continuous recovery does not, and they are specific enough to write down now.

The phase of the edge relative to the receiver's clock is an axis. The transmitter can depart idle at any instant, so the edge can land anywhere within a receiver clock period — including immediately before or after an active edge. Since the receiver's detection is quantised to its own clock, this directly shifts the recorded origin by up to one clock period, and that shift is a real term in Chapter 2.5's budget. A testbench that always starts frames on a convenient clock boundary tests one phase out of many and will not find a design whose margin is marginal.

The first frame after a long idle differs from one in a burst. They exercise different paths into the Idle state of Figure 2 — one after prolonged waiting, one immediately after a frame completed. Both are legal traffic (Chapter 2.2 §5), and a receiver that fails to return cleanly to watching will fail on back-to-back frames specifically.

Frames of different lengths exercise different amounts of prediction. Because N_frame sets how long the open-loop run lasts, the longest supported configuration is the worst case by construction.

And an edge arriving mid-frame is a defined scenario, not an illegal one. The module in §6 clears its count unconditionally on frame_start_i. Whether that is correct behaviour is a design decision with consequences, and a testbench should establish which one the design made rather than assuming it never happens — because on a noisy line, or when a receiver joins a stream already in progress, it does.

None of that is a coverage model. It is the observation that per-frame acquisition puts the acquisition itself under test, repeatedly, in every frame — which is why it deserves more attention than a mechanism that runs once at link-up.

8. What This Means on an FPGA

Three consequences are concrete.

The origin is quantised to the fabric clock. The receiver cannot record the edge at the instant it occurred, only at the next active clock edge — so the recorded origin is late by up to one clock period. At 100 MHz that is at most 10 ns against a T_bit of about 8.68 µs at 115200 baud, roughly 0.12% of an interval, which is small. At a much higher serial rate or a much lower fabric clock the same 10 ns becomes a substantially larger fraction, which is the same scaling argument Chapter 2.2 §2 made about expressing errors as fractions of T_bit.

The detection path adds delay before that. The receive pin is asynchronous to the fabric and must be made safe for synchronous logic before any state decision is taken from it — Module 12 owns that implementation. The relevant fact here is that the boundary adds a small, bounded and known delay, so "the observed edge" in every figure in this module means the edge as it appears after that boundary, not at the pin.

Nothing accumulates across frames, which simplifies the design and complicates the testing. There is no lock state to reach, no acquisition time to wait out, and no condition where the receiver is "not ready yet" after idle. The flip side is that every frame re-runs acquisition, so anything marginal about it is exercised constantly rather than once.

9. Understanding Check

10. Summary

A grid needs a spacing and an origin. The receiver is configured with the spacing and knows nothing about the origin, so it arrives at every frame holding half the information it needs.

The missing half comes from one transition. Transitions inside a frame are not guaranteed — consecutive equal intervals produce no edge — but the departure from the idle level at the start of a frame is, because the framing requires the resting level and the opening level to differ. That single edge is the receiver's entire phase input.

The mechanism is three steps: record the observed instant as an origin, predict the remaining positions by counting locally, and discard the prediction when the frame ends. Nothing is transmitted to assist after the first step, and most of every frame is spent acting on computation rather than evidence — one interval observed, the rest predicted.

The scheme is per frame, not continuous. Unlike a recovery loop that keeps refining its estimate from ongoing transitions, this one acquires once and runs open-loop for the whole frame, so the estimate can only degrade from the moment it is made.

Synchronisation here means one thing only: the receiver's estimate of the transmitted grid is refreshed for this frame. The oscillators are not adjusted, measured or influenced, and nothing persists between frames. "The start bit synchronises the clocks" and "the receiver locks onto the transmitter" are both wrong, and each leads to a specific wrong expectation about error growth, frame length and component choice.

In hardware the origin is a cleared counter rather than a stored timestamp, which gets the same geometry with a small counter and no arithmetic — and the module that does it holds no information about the transmitter at all.

11. What Comes Next

The prediction is built and used open-loop, which raises the question this chapter has carefully left open: how fast does it go wrong? Chapter 2.4 answers it quantitatively — where each endpoint's frequency error comes from, why only the relative error matters, how it accumulates interval by interval across a frame, and why two devices whose errors have opposite signs are the hard case. Chapter 2.5 then spends that accumulated displacement against the margin surrounding each predicted centre, and closes the module by explaining precisely what the end of a frame does and does not restore.

Browse the full path on the UART tutorials index. For a receiver that has a reference delivered to it and must still position it correctly — the same problem with the phase input supplied rather than inferred — see Read Capture.