Idle, Start Bit and Frame Entry

Module 2 built a complete timing model around an object it never named. Chapter 2.1 called it the alignment event; Chapter 2.3 called it the one guaranteed transition and made the receiver's entire phase reference depend on it. Neither chapter said what it actually is, because the framing that produces it had not been introduced.

This module introduces the framing, and this chapter starts where a frame does. The mechanism turns out to be doing two separate jobs, and almost everything engineers get wrong about frame entry comes from treating them as one:

• a transition from the idle state, whose instant fixes the frame's timing origin;
• an interval of known value that follows it, occupying one full bit cell of line time.

An edge has no duration. A bit cell has no instant. The start bit is both, and the rest of this chapter separates them.

1. Idle Is a Precondition, Not an Absence

Chapter 1.3 established that a UART transmitter actively drives its line between frames, and that the resting level and the level that opens a frame must differ. Framing now gives that arrangement its names.

The resting state is the mark condition, conventionally the logical high level, and a transmitter holds it whenever it is not sending. The opening state is the space condition, the logical low level. In this curriculum's waveforms, idle = 1 and the start interval = 0.

Two things follow that are easy to skip past.

Idle is a state the transmitter maintains, not a state the wire falls into. A transmitter that released its output between frames would leave the receiver reading an undefined level, and the framing would have no defined precondition to depart from.

The convention is a framing choice, not a physical fact. Which voltage represents mark depends entirely on the layer below — an RS-232 transceiver inverts the polarity, so the same logical frame appears with opposite voltages at a connector (Chapter 1.4). The framing requirement is only that mark and space are distinguishable and that the frame opens by leaving mark.

2. The Transition and the Interval Are Two Different Things

Here is the distinction the chapter exists for.

The transition is an instant. At some moment the line leaves mark for space. That moment is what Chapter 2.3 turned into a timing origin: the receiver records it, and every position in the frame is counted from it. A transition has no duration and carries no value — it is a time, and nothing else.

The interval is a bit cell. After that moment, the line stays at space for one full bit period. That interval occupies a position on the bit grid (Chapter 2.2), consumes T_bit of line time, and has a defined value throughout.

Both are needed, and neither substitutes for the other.

Read the figure carefully at interval 3. The marker at the boundary is the origin — an instant. The marker at the centre is the bit cell — a duration. They belong to the same start bit and are not the same object.

3. The Entry Contract

Put the two halves together and frame entry becomes a contract between the endpoints, with obligations on each side.

The transmitter undertakes to hold mark whenever it is not sending; to open every frame by transitioning to space; and to hold space for one full bit period before placing anything else on the line.

The receiver undertakes to watch the line while idle; to take the observed transition as its timing origin; to treat the interval that follows as the start position on its reconstructed grid; and to expect the payload from the next position onward.

4. Why a Known Idle State Is Required

Frame entry is defined as a departure, and a departure is only detectable relative to something known. That makes the idle condition load-bearing in a way that is easy to underrate.

It makes the transition detectable. A receiver watching a line with no defined resting state has no event to key off. Chapter 2.2 §3 showed that transitions inside a frame are not guaranteed — consecutive equal payload values produce no edge — so the departure from a known idle is the only transition framing can rely on.

It makes the start interval's value meaningful. Because idle is mark and the start interval is space, the opening bit cell is guaranteed to differ from the state before it. If the framing had opened at mark, a frame beginning after idle would be indistinguishable from continued idle.

And it bounds what a receiver must consider. Between frames the receiver has exactly one thing to look for. That is why the state machine of Chapter 2.3 has an Idle state with a single exit condition.

5. Entry Costs a Bit Period

The start interval occupies one position in every frame, and Chapter 2.2 showed what a position costs: T_bit of conductor time, roughly 8.68 µs at 115200 baud.

Using that chapter's notation, the frame's interval count is the sum of its fields:

N_frame = N_start + N_data + N_parity + N_stop

with N_start = 1, always, in every configuration

The start interval is the only field with a fixed count. Payload width, the presence of parity and the length of the stop condition are all configuration choices — Chapter 3.5 assembles the full space — but every frame opens with exactly one start interval.

That makes it a per-frame tax. A configuration carrying eight payload bits in ten intervals spends one of those ten on entry, and the tax does not shrink when the payload does: a five-bit payload still pays one interval for entry, so the proportion is worse. The full throughput treatment is Chapter 4.1; the point here is only that entry is a field of the frame like any other, and it is counted like one.

6. What This Looks Like in RTL

The line-state convention belongs in one place, named, rather than scattered as literals.

// Synthesizable SystemVerilog — line-state convention and the idle output.
// The frame sequencing that chooses tx_bit is Module 7; this establishes only
// what the line does when no frame is in progress, and what value opens one.
package uart_line_pkg;
    // LOGICAL line states at the controller's own pin. What these become
    // physically is the electrical layer's business (Chapter 1.4) — an
    // RS-232 transceiver inverts both.
    localparam logic UART_MARK  = 1'b1;   // idle, and the stop condition
    localparam logic UART_SPACE = 1'b0;   // the start interval
endpackage

and the transmitter's output while no frame is active:

// Synthesizable SystemVerilog — conceptual output selection only.
// tx_active_i and tx_bit_i come from the frame sequencer of Module 7.
import uart_line_pkg::*;

assign tx_o = tx_active_i ? tx_bit_i : UART_MARK;

Three points are worth extracting.

The idle level is the default, not a state the sequencer must remember to drive. Selecting UART_MARK whenever no frame is active means a transmitter that has just come out of reset, or has finished a frame, holds the correct level without the sequencer doing anything. §4's failure mode is exactly what happens when this is got wrong.

Naming the constants is not cosmetic. A design that writes 1'b1 for idle in one place and 1'b0 for start in another has the polarity convention distributed across the file, and inverting it — which a different electrical layer may require the board to do, not the RTL — becomes an audit rather than an edit.

There is no reset clause here because this is combinational. The register holding tx_bit_i, and the state deciding tx_active_i, are sequential and reset in the sequencer. What this line guarantees is that no reset state of those signals can put the line at space, because tx_active_i low forces mark regardless of tx_bit_i. That is a deliberate property, not an accident of the expression.

7. What This Means for Verification

Frame entry is a small mechanism with a surprisingly wide set of legitimate conditions, and most of them are about when entry happens rather than what it contains.

Entry after arbitrary idle. Idle has no bounded length (Chapter 2.2 §5), so a frame arriving after microseconds and one arriving after hours are both ordinary. Both should be tested; the second exercises whether prolonged idle leaves the receiver in a state that can still detect an entry.

Entry with no idle at all. A frame may begin in the interval immediately after the previous frame's closing condition is satisfied. That is legal traffic, and it is Chapter 3.4's subject — noted here because it means "returns to idle" and "is ready for the next entry" are different claims about a receiver.

The transition's phase relative to the receiver's clock. Established in Chapter 2.3 §7 and repeated here because it belongs to entry specifically: the edge can land anywhere within a receiver clock period, and a testbench that always aligns it to a clock boundary is running with a budget term at its minimum.

Reset released while the line is idle, and while it is not. A receiver coming out of reset onto a quiet line should wait. A receiver coming out of reset partway through someone else's frame will see a payload transition and may take it as an entry. Neither is a bug by itself — but the design has a behaviour in each case, and a testbench should establish which.

The line stuck at space. §4's scenario as a test rather than a debugging story. A receiver should be examined for what it does when the entry condition is continuously satisfied, because the answer determines whether a disconnected cable produces silence or a flood.

Qualification of the transition — deciding that a brief excursion to space is not an entry — is deliberately absent from this list. That is Chapter 5.2, and it changes several of these answers.

8. What This Means on an FPGA

Entry is where the asynchronous input actually matters. The receive pin transitions independently of the fabric clock, and entry is the one moment the receiver must act on a transition rather than on a level it has time to settle on. The input must be made safe for synchronous logic before any state decision is taken from it — Module 12 owns that — and the bounded delay it adds shifts the recorded origin, which Chapter 2.5 counts as a budget term.

A floating receive pin is the most common bring-up fault in this chapter's territory. An unconnected input has no defined level and can drift across the threshold, producing transitions that satisfy the entry condition. Giving the pin a defined level when nothing is attached is a board decision, and it is why a design can appear to receive traffic from a device that is not plugged in.

The transmit pin's reset value is worth checking in the constraints, not just the RTL. §6 guarantees mark from the logic side. If the pin is tri-stated or pulled the other way before configuration completes, the far end sees a line at space during that window — and if it is watching, it will begin decoding.

9. Understanding Check

10. Summary

Module 2's alignment event has a name. A UART frame opens with a start bit, and it does two separable jobs.

Its transition — the instant the line departs mark — is the frame's timing origin, the single piece of phase information the receiver ever gets (Chapter 2.3). Its interval is a full bit cell held at space, occupying a position on the grid and costing T_bit of conductor time. An edge has no duration; a cell has no instant. Conflating them is the source of most confusion about where a frame begins.

Idle is a precondition, not an absence. The transmitter actively holds mark, because entry is defined as a departure and a departure needs something known to depart from. Since transitions inside a frame are not guaranteed, this is the only transition the framing can rely on. The mark/space convention is a framing choice — what those states are physically depends on the electrical layer, which may invert them (Chapter 1.4).

The entry contract binds both sides: the transmitter holds mark when idle, opens with a transition, and holds space for one full bit period; the receiver watches, takes the transition as its origin, treats the following interval as the start position, and expects payload from the next one.

The start bit is not a data bit (its value is fixed and carries no information), not a forwarded clock (one origin, used once, then discarded), and not free (N_start = 1 in every configuration, the only field whose count never varies).

A fault in the idle condition presents as a framing fault, which is why a line resting at space produces an unbroken stream of malformed frames that were never transmitted.

11. What Comes Next

Entry is established, and the receiver's grid is anchored. Chapter 3.2 fills the positions that follow: how a parallel value maps onto consecutive intervals, which end of the value goes first, and why the ordering that looks backwards on a waveform is not a reversal of the byte at all. It is the chapter where bit indexing becomes concrete enough to debug from.

Browse the full path on the UART tutorials index. For the transition treated as a timing object rather than a framing one, Chapter 2.3 is the companion to this chapter and the two are best read together.