Standard Baud Rates and System-Clock Relationships

Chapter 4.1 treated f_baud as a number the configuration supplies. This chapter asks where those particular numbers came from, and the answer turns out to determine the shape of the entire rest of the module.

9,600. 19,200. 38,400. 57,600. 115,200. None is a round decimal figure, and engineers use them without ever asking why. They exist because they are what certain oscillator frequencies divide onto exactly — and the frequencies were chosen for that property.

A modern FPGA fabric clock was chosen for something else entirely. It does not divide onto them exactly, and the reason is not bad luck. It is arithmetic, visible in the prime factorisation, and it cannot be engineered away. Everything in Chapters 4.3 to 4.5 is about what to do with the residue.

1. The Series Is Powers of Two

Look at the classic rates in order and the structure is immediate:

1200  2400  4800  9600  19200  38400  57600  115200
  └──x2──┘  └x2┘  └x2┘   └x2┘   └x2┘         └x2┘

Each is twice its predecessor, with 57,600 and 115,200 continuing the doubling from 28,800. A series related by factors of two is the signature of binary division from a common source: one oscillator, a chain of divide-by-two stages, and every rate available by selecting a tap.

That structure is the whole reason the series looks the way it does. It is not a set of round numbers because round decimal numbers are not what binary division produces.

2. The Frequencies That Divide Exactly

If a design divides a single oscillator down to these rates, the oscillator must be chosen so the divisions come out whole. 1.8432 MHz is the canonical example, and the arithmetic shows why:

Every row is a whole number. And the right-hand column — the divisor remaining if a receiver takes sixteen samples per bit interval, an arrangement Module 5 examines — is also whole in every row, down to 1 at 115,200.

That is not a coincidence, it is the design intent: 1,843,200 = 115,200 × 16. The frequency exists so that the fastest rate in the series needs no division at all once the sampling factor is accounted for, and every slower rate falls out by halving.

Larger members of the same family behave identically because they are multiples: 14.7456 MHz is exactly 8 × 1.8432 MHz, so it divides onto 9,600 (by 1,536) and 115,200 (by 128) exactly, with the same clean structure.

3. The Exactness Criterion

State the condition precisely, because it is the whole content of this chapter:

f_clk / f_baud  is a whole number   if and only if   f_baud divides f_clk

Equivalently, in prime factors: every prime power in f_baud must appear in f_clk to at least the same exponent. When it does not, the ratio is a fraction in lowest terms and no integer counter can represent it.

Apply it to the pairing from Chapter 2.2:

100,000,000 = 2^8  x  5^8
    115,200 = 2^9  x  3^2  x  5^2

Two independent failures. The rate needs 2^9 and the clock supplies only 2^8. The rate needs 3^2 and the clock supplies no factor of three at all. Either alone makes exact division impossible.

The exact ratio, in lowest terms:

gcd(100,000,000, 115,200) = 6,400

100,000,000 / 115,200 = 15,625 / 18
                      = 868.0555...

A denominator of 18 means the pattern only closes after 18 bit intervals — a fact Chapter 4.4 turns into hardware. It is not a rounding artefact; it is the exact rational form of the ratio.

Across the pairings an engineer actually meets:

Two patterns are worth reading off it.

The serial-family crystals are exact on the classic series and fail on 1 Mbaud, because 1,000,000 contains 5^6 and they do not.

The round fabric clocks are the mirror image: exact on 1 Mbaud, which is a decimal figure made of the same primes, and inexact on every member of the classic series. A design at 1 Mbaud from a 100 MHz clock has zero divider error; the same design at 115,200 does not.

4. Knowing Where You Stand, at Elaboration

Whether a given pairing is exact, and by how much it misses, is known at build time and is worth reporting rather than discovering later.

// Synthesizable SystemVerilog — elaboration-time reporting only. Infers no
// hardware. The divider this describes is built in Module 8; the error it
// leaves is quantified in Chapter 4.3. What this block does is make the
// arithmetic visible in the build log instead of implicit in a constant.
module uart_rate_report #(
    parameter int unsigned CLK_HZ  = 100_000_000,
    parameter int unsigned BAUD_HZ = 115_200
) ();
    // Exactness test, straight from §3: the ratio is whole iff the remainder
    // is zero. Integer modulo, evaluated by the tool.
    localparam bit EXACT = (CLK_HZ % BAUD_HZ == 0);

    // Truncating division — the floor divisor. Chapter 4.3 shows this is a
    // policy choice and not always the right one.
    localparam int unsigned N_FLOOR = CLK_HZ / BAUD_HZ;

    initial begin
        // Legality before anything else: a divisor below one cannot be
        // counted, and both zero parameters make the arithmetic meaningless.
        if (BAUD_HZ == 0 || CLK_HZ == 0)
            $fatal(1, "uart_rate_report: CLK_HZ and BAUD_HZ must be non-zero");
        if (N_FLOOR < 1)
            $fatal(1, "uart_rate_report: BAUD_HZ (%0d) exceeds CLK_HZ (%0d) - no divisor exists",
                   BAUD_HZ, CLK_HZ);

        if (EXACT)
            $info("uart_rate_report: %0d Hz / %0d baud divides exactly, N = %0d",
                  CLK_HZ, BAUD_HZ, N_FLOOR);
        else
            $warning("uart_rate_report: %0d Hz / %0d baud is NOT exact (floor N = %0d, remainder %0d) - see rate error",
                     CLK_HZ, BAUD_HZ, N_FLOOR, CLK_HZ % BAUD_HZ);
    end
endmodule

Four points, each of which recurs in the RTL of the following chapters.

CLK_HZ % BAUD_HZ == 0 is the criterion from §3, expressed directly. Nothing about it is approximate: it is integer modulo evaluated once by the tool.

Parameter legality is checked before the arithmetic uses it. BAUD_HZ == 0 would make the modulo and the division meaningless, and a requested rate above the clock produces a floor divisor of zero — a counter that must count to −1, which is not a thing. Chapter 4.3 develops why the N < 2 region is dangerous rather than merely degenerate. Catching it at elaboration turns an impossible design into a build failure instead of a silent one.

$warning rather than $fatal for inexactness, because §3 established that inexact is the normal case. A design that refused to build on an inexact ratio would refuse almost every real pairing. What is valuable is that the fact appears in the log, so nobody discovers it from a logic-analyser capture.

The block infers nothing. Everything is localparam and an initial block, both resolved during elaboration. The netlist is empty, which is why this can sit in a design permanently at no cost.

5. What This Means for Verification

The clock/rate pairing is a verification axis, and its interesting values are not random. A design supporting several rates from one fabric clock has a different divider — and a different error — at each. The cases that matter are the extremes of that set: the pairing with the largest fractional remainder carries the worst error, and any pairing that happens to be exact is the only one where the divider contributes nothing.

Exact pairings are dangerously reassuring. A design verified only at 1 Mbaud from a 100 MHz clock has been tested with a divider error of exactly zero, so every downstream timing margin looks generous. The same design at 115,200 has a non-zero error the test never saw. If a design supports both, the inexact rate is the one that must be verified, and the exact one proves almost nothing about it.

A testbench should recompute the expectation rather than inherit it. The expected interval is a function of f_clk and the divider policy, so a checker that hard-codes cycles per bit is verifying one pairing and will report a false failure on the next. The arithmetic is the same modulo and division as §4.

6. What This Means on an FPGA

Check the pairing before choosing the rate, not after. The elaboration report of §4 costs nothing and tells you immediately whether the design is in the exact case or the ordinary one.

If a rate can be chosen freely, prefer one the clock divides. A link between two parts of your own system — an FPGA and an MCU you also control — has no obligation to use a historic rate at all. At 100 MHz, 1 Mbaud divides exactly by 100 and carries zero divider error, where 115,200 does not. A rate chosen for arithmetic rather than tradition removes one budget term permanently.

If the rate is fixed by the far end, the ratio is an input, not a choice. A USB-to-serial bridge or a host expecting a standard rate settles the question, and the design's job is to represent that rate as accurately as its clock allows — which is Chapter 4.3.

A dedicated serial oscillator is a real option and usually the wrong one. It buys exactness at the cost of a component, a clock domain, and the crossing between it and the fabric. For a debug console the error from an inexact divider is typically far below what the budget of Chapter 4.5 can absorb, and the extra domain is a larger problem than the one it solves.

7. Understanding Check

8. Summary

The standard rates form a power-of-two series because they were produced by binary division from one oscillator. They are not round decimal figures because binary division does not produce round decimal figures.

Certain oscillator frequencies exist precisely so that the division comes out whole. 1.8432 MHz = 115,200 × 16 divides exactly onto every member of the series, and its divisors remain whole even after a sixteen-sample-per-interval receiver takes its share; 14.7456 MHz is eight times the same frequency and behaves identically.

The criterion is simple: f_clk / f_baud is whole exactly when f_baud divides f_clk, which in prime factors means every prime power in the rate must appear in the clock. 100 MHz fails against 115,200 twice over — it supplies 2^8 where 2^9 is needed, and no factor of three at all — so the exact ratio is 15,625 / 18, a fraction whose denominator of 18 reappears as hardware in Chapter 4.4.

Modern fabric clocks and the classic rate series are mirror images: the serial-family crystals are exact on the series and fail on 1 Mbaud, while round fabric clocks are exact on 1 Mbaud and fail on the series.

And the pairing is usually not a choice. The clock serves something else, the rate is fixed by the far end, and an inexact ratio is the normal input condition rather than a defect. What follows is the engineering: what error the chosen representation leaves, and whether the budget can absorb it.

9. What Comes Next

The ratio is a fraction and a counter holds an integer. Chapter 4.3 confronts that directly: how the divisor is chosen, why floor, ceiling and nearest are three different policies with measurably different outcomes, what actual rate each produces, and why the resulting error should be expressed as a fraction of a bit period rather than as a bare percentage.

Browse the full path on the UART tutorials index. For the same divide-a-clock-onto-a-required-rate problem where the residue is handled by a different mechanism entirely, see Clock Dividers and Timers.