Sampling Centres and the Timing Margin Budget

Chapter 2.4 produced a displacement, Δt(n) ≈ n x ε_rel x T_bit, and deliberately declined to say whether it is survivable. This chapter answers that, and in answering it closes the module.

The question is sharper than "how much error is allowed", and the sharper form is the useful one:

How far may the receiver's sampling instant move away from where the transmitter placed a bit, before the receiver decides on the wrong one?

Answering it requires two things this module has built separately and not yet combined: the geometry of an interval, which says where there is room to be wrong, and the budget, which enumerates everything already spending that room before drift gets any. The module then ends on the misconception it has been circling since Chapter 2.1 — what the end of a frame actually restores.

1. Where There Is Room to Be Wrong

Chapter 2.2 §3 gave the geometry. Interval k spans [k x T_bit, (k+1) x T_bit), and the conductor holds one value for the whole of it. So a receiver sampling anywhere inside that span reads the correct value, and a receiver sampling outside it reads a neighbouring interval instead.

That makes the question positional. Sampling at some offset s from the interval's start boundary, the distance to the two hazards is:

distance back to the previous boundary  =  s
distance forward to the next boundary   =  T_bit − s

The smaller of the two is what the receiver can afford to lose. Maximising it means making them equal:

s = T_bit − s
2s = T_bit
s  = 0.5 x T_bit

The centre maximises the minimum distance to a hazard, and the resulting margin is half a bit period in either direction. That is the entire argument for centre sampling, and it is geometry rather than convention.

2. The Half-Bit Is a Budget, Not an Allowance

0.5 x T_bit is the geometric room available. It is not what drift may consume, because drift is not the only claimant. Several effects displace the sampling instant from the ideal centre, and they are spent from the same half-bit.

   0.5 x T_bit                      geometric room, one side

 − origin uncertainty               where the receiver THINKS the frame began
 − interval construction error      its bit interval is not exactly T_bit
 − accumulated relative drift       n x ε_rel x T_bit, from Chapter 2.4
 − decision-mechanism uncertainty   the sampling window is not an instant
 − implementation margin            the part deliberately left unspent

 = remaining margin at interval n

Each term has an owner in this curriculum, and three of them have already appeared.

Origin uncertainty comes from Chapter 2.3 §8. The receiver cannot record the opening edge at the instant it occurs, only at its next clock edge, so the recorded origin is late by up to one clock period — and the input boundary that makes the pin safe for synchronous logic adds a further bounded delay before that. Both shift every predicted position in the frame by the same amount.

Interval construction error comes from Chapter 2.2 §6. The receiver builds its interval from a whole number of clock cycles, and F_clk / f_baud is essentially never whole, so its interval differs systematically from T_bit. Note that this term is already inside ε_RX, and therefore inside ε_rel — it is listed separately only because engineers routinely forget it is there when they estimate a budget from crystal tolerances alone.

Accumulated drift is Chapter 2.4's result, and it is the only term that grows within a frame.

Decision-mechanism uncertainty belongs to Module 5. A receiver does not sample at a dimensionless instant; whatever strategy it uses occupies a window and positions that window with its own granularity.

Implementation margin is what a competent design leaves unspent, so that a part at the edge of its specification, or a temperature at the edge of the range, does not consume the last of the budget.

3. The Last Interval Is Where It Fails

Four of the five terms are roughly constant across a frame. Drift is not — it is linear in the interval index, so the remaining margin shrinks monotonically as the frame proceeds:

remaining(n) ≈ 0.5 x T_bit − (fixed terms) − n x ε_rel x T_bit

The smallest value occurs at the largest n. So:

The budget is evaluated at the last interval of the frame, not the first, and a design that satisfies it there satisfies it everywhere. Equivalently, the first symptom of an inadequate budget appears at the end of a frame — the Chapter 2.4 §7 failure signature, now explained rather than merely observed.

This also gives the module's central trade its final form. Since the worst case sits at n = N_frame − 1, a design choosing a longer frame moves its own worst case further out and spends more of its budget — which is why Chapter 2.2 insisted on carrying N_frame as a parameter rather than accepting ten as a constant.

4. What the End of a Frame Actually Does

This is the correction the module has been building toward, and it is worth stating against the belief it replaces.

The belief: the stop bit resynchronises the receiver, which is why drift does not accumulate forever.

What the closing interval actually does. It holds the line at the idle level for at least its configured duration. That gives three things: the frame a defined end, separation from whatever follows, and a guarantee that the line is at the idle level so the next frame's departure from idle is detectable. A receiver may also check that the line is at the expected level there, and use a violation as evidence that the frame was malformed — Module 3 and Module 9 own that.

What it does not do. It does not adjust the receiver's timing, does not measure anything, and does not remove the displacement accumulated during the frame. At the moment the closing interval is sampled, the accumulated drift is at its maximum — that sample is the worst case of §3. Nothing about the interval's existence reduces it.

What actually re-establishes alignment is the next frame's departure from idle, exactly as Chapter 2.3 described. A new origin is recorded, a new prediction is built, and displacement starts from zero again — because the old prediction was discarded, not because anything was corrected.

The distinction has a testable consequence. If the closing interval resynchronised anything, back-to-back frames would behave differently from frames separated by a long idle, since one provides more of it than the other. They do not: what matters in both cases is the next departure from idle, and the length of the gap before it is irrelevant (Chapter 2.2 §5).

5. The Budget as a Design Constraint

The budget is an analysis rather than a block of hardware, so this chapter adds no datapath. What it can add is the point where the analysis becomes a check — an elaboration-time guard that refuses to build a design whose parameters cannot work.

// Synthesizable SystemVerilog — elaboration-time check only. No hardware
// is inferred by the generate block below; it runs in the tool.
//
// The budget terms here are the ones a design KNOWS at elaboration. The
// part-dependent terms (oscillator tolerance over temperature) and the
// strategy-dependent ones (Module 5) are supplied as parameters by the
// integrator, because only they know the parts and the environment.
// Chapter 4.5 develops the full budget this check enforces.
module uart_timing_check #(
    parameter int unsigned CLK_HZ      = 100_000_000,
    parameter int unsigned BAUD        = 115_200,
    parameter int unsigned N_FRAME     = 10,

    // Budget inputs, in parts per million, supplied by the integrator.
    parameter int unsigned EPS_REL_PPM = 20_000,  // 2% — BOTH ends combined
    parameter int unsigned FIXED_PPM   = 40_000   // 4% — origin uncertainty,
                                                  // decision window, reserve
) ();
    // Worst case sits at the LAST interval (§3), not the first.
    localparam int unsigned WORST_N  = N_FRAME - 1;

    // Everything in ppm of a bit period, so no real arithmetic is needed.
    localparam int unsigned HALF_BIT = 500_000;                  // 0.5 T_bit
    localparam int unsigned DRIFT    = WORST_N * EPS_REL_PPM;
    localparam int unsigned SPENT    = DRIFT + FIXED_PPM;

    initial begin
        if (SPENT >= HALF_BIT) begin
            $fatal(1, "uart_timing_check: budget exhausted — %0d ppm spent of %0d ppm available at interval %0d",
                   SPENT, HALF_BIT, WORST_N);
        end
    end
endmodule

The value is in what the parameters force an integrator to state out loud.

EPS_REL_PPM is the combined figure, not one endpoint's. The comment says so because Chapter 2.4 §4 showed this is where the factor-of-two error enters: two endpoints each within 1% can be 2% apart. A parameter named for one side invites exactly that mistake.

WORST_N is N_FRAME − 1. Encoding §3's result in the check means a design that later lengthens its frames re-evaluates its budget automatically at elaboration rather than failing in the field.

Everything is ppm of a bit period. Integer arithmetic throughout, no reals, and the units are the fractional ones the whole module has used — so the numbers in the error message are directly comparable with the tables in Chapter 2.4.

$fatal in an initial block infers nothing. It is evaluated during elaboration and contributes no logic; the module is empty in the netlist. The illustrative default values are not recommendations — they exist so the example is concrete, and a real integration replaces both with figures from its own datasheet and its own sampling strategy.

What it deliberately cannot check. Whether EPS_REL_PPM is honest. A design whose integrator supplies an optimistic number passes elaboration and fails in the field, which is why the datasheet-over-temperature discipline of Chapter 2.4 §1 matters more than the check does.

6. What This Means for Verification

The budget turns a vague question into a computed boundary, and a computed boundary is a test plan.

Test at the boundary the design claims, not the one a textbook quotes. Every design has its own budget because §2's terms differ between designs. The cases worth running are nominal, comfortably inside, just inside, and just outside the figure the design itself computes — with the outside case expected to fail, and checked that it fails the way the design says it will.

The last interval is the observation point. Because margin shrinks monotonically, a failure appears at the end of a frame first. A checker that only compares final byte values sees a corrupted result; one that knows which interval failed distinguishes an inadequate budget from a framing bug, and the difference is diagnostically enormous.

The maximum supported frame length is the worst case by construction, so it is the configuration the boundary cases should use. Testing the budget at the shortest frame establishes almost nothing.

Vary the origin's phase as an independent axis. Chapter 2.3 §7 made this point; §2 explains why it belongs in the budget rather than merely in the stimulus. Origin uncertainty is a fixed term, so a testbench that always presents the opening edge on a clock boundary is running with one budget term set to its minimum and will over-estimate the design's real margin.

And check the stop-interval belief directly. Because §4 says back-to-back frames and long-idle frames should behave identically, that is a property worth asserting: a receiver whose performance differs between the two has a timing dependence on the gap that the model says should not exist.

7. What This Means on an FPGA

Two terms shrink when the ratio shrinks. Origin uncertainty is bounded by one fabric clock period and interval construction error by the discarded fraction of F_clk / f_baud. Both are absolute quantities measured against a T_bit that gets smaller as the rate rises — so pushing the serial rate up, or moving to a slower fabric clock, grows both terms as a share of the budget. A design comfortable at 115200 from 100 MHz may have a materially different budget at 1 Mbaud.

Temperature is where the budget is actually spent. The bench is the most forgiving condition in the product's life. A budget computed from typical figures is not a budget.

The reserve term is the one under your control. Origin uncertainty and the decision window follow from the clock and the strategy. The crystal follows from the bill of materials. What an engineer chooses is how much of the half-bit to leave unspent — and leaving none is how a design that passed every test fails on the tenth production board.

8. Understanding Check

9. Summary

The conductor holds one value across a whole interval, so the question is positional: how far can the sampling instant move before it lands in a neighbour. At offset s the distances to the two hazards are s and T_bit − s, and the smaller is maximised when they are equal — giving s = 0.5 x T_bit and half a bit period of room in either direction. That is the argument for centre sampling, and it is geometry, not convention. It does not make exact 50% sampling a requirement.

The half-bit is a budget with five claimants: origin uncertainty, interval construction error, accumulated relative drift, decision-mechanism uncertainty, and the reserve a competent design leaves unspent. Only drift grows within a frame, so remaining margin falls linearly and the last interval is the worst case — which is why an inadequate budget first shows itself at the end of a frame, and why the budget must be evaluated at n = N_frame − 1.

Because four of the five terms are design- and part-dependent, no universal tolerance figure exists. What transfers is the structure; the number must be computed per design, which Chapter 4.5 does.

Finally, the correction this module has been building toward. The closing interval of a frame provides a defined end, separation, a guaranteed idle level for the next detection, and a checkable condition — and it resynchronises nothing. Accumulated displacement is at its maximum when it is sampled. What re-establishes alignment is the next frame's departure from idle, which supplies a new origin so displacement starts from zero. The phase reference resets; the oscillator errors do not.

10. Where Module 2 Leaves You

Five chapters have built one argument.

Two independent clocks can communicate because only a finite, per-frame agreement is required — the four-term bargain of Chapter 2.1, whose load-bearing term is that a frame ends. To reason about that agreement quantitatively, Chapter 2.2 converted a baud figure into T_bit, the grid of boundaries and centres, and T_frame = N_frame x T_bit — and found that a real system clock does not divide evenly onto a serial rate, introducing a third error source before any component tolerance is considered. Chapter 2.3 supplied the grid's origin from the single guaranteed transition per frame, and established that the reconstruction is per-frame and open-loop, so nothing about the two clocks is ever synchronised. Chapter 2.4 quantified how that open-loop prediction degrades: only the relative error matters, opposite signs are the hard case, and displacement grows as n x ε_rel x T_bit — linearly in frame length. And this chapter spent that displacement against the half-bit of geometric room, found four other claimants on the same budget, and identified the last interval of the frame as where it runs out.

An engineer holding that chain can look at a fabric clock, a configured rate and a frame length and reason about whether the link will work — and knows which datasheet figures they still need. That is what Module 2 was for.

11. What Comes Next

Every chapter in this module has referred to "the frame" while treating its contents as out of scope. Module 3 opens it: what the opening interval is, how the payload intervals are ordered, what an optional interval may carry, what the closing interval must satisfy, and how the configuration space of all four is described. The timing model built here does not change — it becomes the thing the frame's structure is designed against.

After that, Module 4 returns to this module's unfinished arithmetic and derives the budget properly for a stated design, and Module 5 builds the decision mechanism whose uncertainty appeared in §2 as a term with no number.

Browse the full path on the UART tutorials index. For a sampling budget assembled the same way but closed by training rather than by ending a frame, see Read Capture and Write Levelling.