UART — Tutorials · VLSI Mentor

96Total chapters

18Modules

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18 / 18Active modules

Async first, framing later

Clock-mismatch tolerance, drift, and oversampling before framing — the mental model that turns UART from a packet diagram into an engineering discipline.

Engineering reasoning

Timing analysis, RX and TX architecture, CDC and reset, verification, and waveform debugging — the reasoning engineers are actually judged on, taught as engineering rather than as an answer bank.

Design → verify → debug

RTL templates (RX FSM, TX FSM, baud generator, FIFOs, RTS/CTS), SVA / UVM verification, and waveform-based debugging — the full engineering loop.

UART Complete Curriculum

Your Learning Roadmap

96 chapters · 18 modules — async serial, oversampling, framing, flow control, and FIFOs.

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Module 1

UART Mental Model & System Context

1.1What a UART Actually Is 1.2Synchronous vs Asynchronous Serial Links 1.3The UART Link: TX, RX, Idle and Full Duplex 1.4UART vs RS-232, RS-485 and the Physical Layer 1.5Where UART Lives: Debug Consoles, Boot and Bring-Up 1.6UART vs Other Interfaces: Choosing the Right Link

Module 2

Asynchronous Serial Timing

2.1Why Two Independent Clocks Can Still Communicate 2.2Bit Time, the Bit Grid and Frame Duration 2.3Start-Bit Synchronisation and Per-Frame Timing Recovery 2.4Clock Drift, ppm and Accumulated Timing Error 2.5Sampling Centres and the Timing Margin Budget

Module 3

UART Frame Format & Configuration

3.1Idle, Start Bit and Frame Entry 3.2Data Bits and LSB-First Transmission 3.3Parity Generation, Checking and Error Detection 3.4Stop Bits, Frame Boundaries and Back-to-Back Frames 3.5Frame Configurations: 8N1 and the Configuration Space

Module 4

Baud Rate, Clock Error & Timing Budget

4.1Baud Rate, Bit Rate and Real Throughput 4.2Standard Baud Rates and System-Clock Relationships 4.3Integer Dividers and Baud-Rate Error 4.4Fractional Baud Generation 4.5The UART Timing Budget: How Much Mismatch a Frame Survives

Module 5

Receiver Sampling & Oversampling

5.1Why Receiving Is Harder Than Transmitting 5.2Start-Edge Detection and Start-Bit Validation 5.3Oversampling Strategies: 8×, 16× and the Alternatives 5.4Majority Voting, Noise Rejection and the Sampling Window 5.5Sampling Under Clock Mismatch

Module 6

UART Receiver Architecture

6.1RX Datapath and Block Partitioning 6.2The RX FSM 6.3Sample Counters, Bit Counters and the RX Shift Register 6.4Parity Check, Stop-Bit Validation and Error Status 6.5Data-Valid Generation and the Receiver Handshake 6.6Complete RX RTL Architecture

Module 7

UART Transmitter Architecture

7.1TX Datapath and Parallel-to-Serial Conversion 7.2The TX FSM and Frame Sequencing 7.3Baud Enable and TX Bit Timing 7.4Ready/Busy Handshake and Back-to-Back Frames 7.5Complete TX RTL Architecture and Configuration Handling

Module 8

Baud Generator RTL

8.1Clock Enable vs Generated Clock 8.2Integer Divider RTL 8.3Fractional Accumulator Baud Generation 8.4RX and TX Baud Timing: One Generator or Two?8.5Parameterisation, Reset and Error Reporting

Module 9

UART Errors, Breaks & Recovery

9.1Framing Errors 9.2Parity Errors and the Limits of Detection 9.3Overrun, Underrun and Data Loss 9.4Break Conditions: Generation and Detection 9.5False Starts, Noise and Malformed Frames 9.6Error Status, Sticky Flags and Receiver Re-Synchronisation

Module 10

FIFOs, Backpressure & Flow Control

10.1Why UART IP Needs FIFOs 10.2TX and RX FIFO Architecture 10.3Thresholds, Watermarks and Trigger Levels 10.4Overflow, Overrun and Backpressure 10.5RTS/CTS Hardware Flow Control 10.6XON/XOFF Software Flow Control and Its Limits

Module 11

Building a Complete UART IP

11.1Top-Level UART IP Architecture 11.2Integrating TX, RX, Baud Generation and FIFOs 11.3Configuration, Control and Status Plumbing 11.4Parameterisation and Reusable RTL Organisation 11.5Loopback, Test Modes and Built-In Self-Check

Module 12

CDC, Reset & Implementation Concerns

12.1Metastability and the Asynchronous RX Input 12.2Synchroniser Placement and Edge Detection After Synchronisation 12.3UART Clock Domains: What Is and Is Not CDC 12.4Reset Strategy and Reset During Active Traffic 12.5Synthesis and Timing Constraints 12.6FPGA and ASIC Implementation Differences

Module 13

Register Interface, Interrupts & DMA

13.1UART as a Memory-Mapped Peripheral 13.2Control, Configuration, Data and Status Registers 13.3Interrupts: Sources, Enables and Clear Semantics 13.4DMA Interaction and Bulk Transfer 13.5Bus Attachment and Integration Concerns

Module 14

UART Verification Strategy

14.1Building a UART Verification Plan 14.2Stimulus Architecture and the Serial BFM 14.3Verifying the Transmitter 14.4Verifying the Receiver 14.5Monitor, Reference Model and Scoreboard 14.6Negative Testing and Corner-Case Strategy

Module 15

Assertions, Coverage & Error Injection

15.1UART Properties Worth Asserting 15.2Writing UART Assertions for TX, RX and FIFOs 15.3Functional Coverage and Configuration Crosses 15.4Error Injection and Corrupted-Frame Testing 15.5Baud Mismatch, Reset-During-Traffic and Boundary Stress

Module 16

UVM UART Verification Environment

16.1UART UVM Environment Architecture 16.2Sequence Item and Sequence Library 16.3The Driver and the Bit-Timing Problem 16.4Monitor, Agent and Active/Passive Reuse 16.5Reference Model, Scoreboard and Coverage Collector

Module 17

Waveform Debugging & Silicon Bring-Up

17.1Reading a UART Waveform as Evidence 17.2Baud Mismatch and Sampling-Error Signatures 17.3Bit Order, Parity and Framing Failure Signatures 17.4Missing Start Bits, False Starts and Noise 17.5FIFO Overrun and Flow-Control Failures 17.6FPGA Debug, ILA Capture and Board Bring-Up

Module 18

Engineering Case Studies & Design Review

18.1Case Study: FPGA UART Implementation and Bring-Up 18.2Case Study: SoC Boot and Debug Console UART 18.3Case Study: Verifying and Debugging a Production UART IP 18.4UART Design Review: The Questions a Reviewer Asks