UART vs RS-232, RS-485 and the Physical Layer

Three chapters have now described a UART as logic: a converter between parallel data and timed activity, a receiver that builds its own sampling reference, a link of two one-way conductors. Every one of those descriptions stopped short of saying what the conductors physically carry, and Chapter 1.3 explicitly deferred the question of how many devices can share them.

This chapter answers both, and the answer is a layering. The confusion it clears up is the most persistent one in the subject — that UART and RS-232 are two names for the same thing, or that RS-485 is "UART with different voltages". Neither is true, and the reason they are not true is worth more than the correction itself: the framing and the electrical layer are independent choices, and almost everything an engineer cares about at the system level — reach, noise immunity, how many devices, whether they can all talk at once — is decided by the layer the framing knows nothing about.

1. The Stack

Start by separating things that are usually met together. A working serial connection is a stack of independent decisions, and each layer can be changed without touching the ones above it.

Two observations about the figure carry the chapter.

The boundary is the logic-level pins. Above that line, everything is the digital design covered by this curriculum. Below it, everything is a separate discipline with its own standards and its own failure modes. A UART controller drives a level on a pin; it has no representation anywhere of what that level becomes afterwards.

The transceiver layer is optional. Two devices on the same board, at the same supply voltage, connect their logic-level pins directly. That is a complete, working UART link with no transceiver at all, and it is the arrangement most FPGA and embedded designs actually use.

2. What a Transceiver Does — and What It Preserves

A transceiver is a translator, and being precise about what it translates is what makes the layering usable.

It changes the electrical representation of each bit: the voltages, the drive characteristics, whether the signal is carried on one conductor referenced to ground or as a difference between two.

It does not change the bit pattern, the order of bits, the duration of a bit, or when a transmission begins. A transceiver has no idea what a frame is. It is a level-by-level translator with a propagation delay, not a protocol participant.

3. Logic-Level UART — the Default Case

When both devices sit at the same supply voltage, the controller's pins connect directly.

The signalling is single-ended: each conductor carries a voltage referenced to a ground shared by both devices. A level near the supply rail is one logic state, a level near ground is the other, and the receiver's input threshold sits somewhere between. This is ordinary CMOS-family digital signalling, the same as any other logic signal on the board.

Two properties follow, and both are limits rather than features.

Reach is short. A single-ended signal referenced to a shared ground is vulnerable to anything that disturbs either the signal or the ground reference between the two devices. Over a board trace that is a non-issue. Over a long cable between separately powered equipment, both the coupled noise and the difference between the two grounds become problems the signalling has no mechanism to reject.

The supply voltages must be compatible. Two devices at different supply voltages cannot simply be wired together: the lower-voltage device may not recognise the higher one's levels as valid, and — the direction that actually destroys hardware — the higher-voltage device's output may exceed what the lower one's input can tolerate. This is a routine integration issue with routine answers, and it is the most common reason a level shifter appears on a board even when no protocol translation is needed at all.

4. RS-232 — a Different Electrical Layer for the Same Framing

RS-232 (standardised as TIA/EIA-232, and revised several times) is a physical-layer and interface standard. It specifies electrical characteristics, a set of signal functions, and mechanical connector arrangements. It is not a framing standard, and it does not define what a byte looks like on the wire.

Three differences from logic-level signalling matter to a digital engineer.

The levels are bipolar and larger. Where a logic-level signal swings between ground and the supply, an RS-232 line swings between a substantial negative and a substantial positive voltage, with a wide undefined band between the receiver's thresholds. The larger swing and the wide dead band are what buy noise immunity over a cable.

The polarity is inverted relative to logic level. The RS-232 mark state — the one a UART holds while idle — is the negative voltage, and space is positive. A transceiver performs this inversion in both directions, which is why a correctly installed pair of transceivers is invisible to the controller and a single one is catastrophic: invert one side only and every bit, including the idle level, is wrong.

It is single-ended and defined for one device at each end. Each signal is one conductor referenced to a shared ground, and the standard describes an interface between two pieces of equipment.

5. RS-485 — Where Topology Actually Comes From

RS-485 (TIA/EIA-485) is a different electrical layer again, and it is the one that makes the layering argument concrete, because it changes something engineers routinely believe UART forbids.

The signalling is differential. A bit is carried as the difference between two conductors rather than as a voltage referenced to ground. Noise that couples into a twisted pair tends to affect both conductors similarly, and a differential receiver responds to the difference, so common disturbance is largely rejected. The same mechanism tolerates a modest difference between the two devices' ground potentials. This is why RS-485 reaches far further, in worse environments, than either of the previous options.

Multiple drivers can share one pair. A differential driver can be disabled — placed in a high-impedance state where it is not driving the pair at all. That single capability changes the connectivity model: several devices can be attached to the same pair, with exactly one driving at any moment and the rest listening.

And there it is. A UART controller — the same controller, with the same framing — connected through RS-485 transceivers can sit on a multidrop network. The framing did not change. The electrical layer did.

What the framing still does not provide

The multidrop case is where engineers most often over-read what they have gained, so state the limit precisely. RS-485 makes it electrically possible for many devices to share a pair. It supplies nothing else that a shared medium needs:

• No addressing. Nothing in a UART frame identifies a recipient.
• No arbitration. Nothing decides whose turn it is to enable a driver.
• No collision detection. Two drivers enabled at once corrupt the pair, and the framing has no way to notice or recover.

Those are supplied by a protocol layered on top — a higher-level scheme that assigns addresses and decides who may transmit, with the bytes it exchanges carried by ordinary UART framing. Industrial fieldbus protocols built over RS-485 exist precisely to fill this gap. The division of labour is clean and worth memorising: the transceiver makes sharing physically possible, a higher-layer protocol makes it orderly, and the UART in the middle carries bytes without knowing either.

6. The One Place the Electrical Layer Reaches Back Into the Design

Everything so far has kept the controller ignorant of what is below it. There is one arrangement where that is not quite true, and it is a genuine design requirement rather than a detail.

A two-wire RS-485 arrangement shares one pair for both directions. Only one device may drive at a time, so each device's transmitter must enable its driver before transmitting and disable it afterwards. That enable is a signal the digital design has to produce — and its timing is a real constraint with a real failure mode on each side:

• Assert too late and the beginning of the transmission is driven into a disabled transceiver. The first part of the frame never reaches the pair.
• De-assert too early and the end of the transmission is truncated the same way — and because the last part of a frame is what a receiver uses to judge that the frame was well formed, this usually presents as a framing error rather than as missing data.
• De-assert too late and this device is still driving when another begins, corrupting the pair for both.

The safe formulation is that the enable must be asserted before the first bit reaches the pin and held until the last bit has completed its full duration — not merely until the transmitter's internal state machine has finished. Those are different instants, and the difference is where this bug lives.

// Synthesizable SystemVerilog — transceiver control, not the TX engine.
// Shows only WHERE the enable comes from and what it must respect.
// The transmitter that produces tx_busy_i is Module 7; the bit timing
// that makes "last bit complete" a definite instant is Module 4.
module rs485_de_ctrl (
    input  logic clk,
    input  logic rst_n,
    input  logic tx_busy_i,   // high while a frame is on the wire,
                              // INCLUDING the final bit's full duration
    output logic de_o         // drives the transceiver's driver-enable pin
);
    always_ff @(posedge clk or negedge rst_n) begin
        if (!rst_n) de_o <= 1'b0;   // released on reset: never drive a
                                    // shared pair before the design is ready
        else        de_o <= tx_busy_i;
    end
endmodule

The block is deliberately almost empty, because its content is not the logic — it is the contract on tx_busy_i.

What the block holds. One flop. It registers the enable so the output is glitch-free and has a defined relationship to the clock.

The timing assumption. de_o follows tx_busy_i by one clock cycle. That is acceptable only because a clock cycle is far shorter than a bit period on any sane configuration — an assumption that holds by orders of magnitude, and one Module 4 quantifies rather than assumes.

The reset behaviour is the interesting decision. de_o resets to disabled, not enabled. On a shared pair this matters more than usual: a device coming out of reset with its driver enabled corrupts traffic between two entirely different devices. Reset-to-safe is the rule whenever an output affects a medium the design does not own.

The corner case the module cannot fix. If tx_busy_i falls when the transmitter's state machine completes rather than when the final bit has finished on the wire, this block faithfully de-asserts too early and truncates every frame. The defect is upstream, and no amount of logic here repairs it — which is exactly why the port comment states the contract rather than merely naming the signal.

What synthesis produces. A single flip-flop with an asynchronous reset and no combinational logic on its input. If a synthesis report shows anything more, something has been added that does not belong.

For a four-wire RS-485 arrangement — separate pairs per direction — none of this applies, and the controller returns to being fully ignorant of the layer below. Which arrangement a product uses is an integration decision, and a design intended for reuse exposes the enable and lets the integrator ignore it.

7. Verification and FPGA Consequences

What is inside the verification boundary and what is not. A UART core's testbench verifies framing and timing at the logic-level pins. Transceiver behaviour — levels, thresholds, propagation delay, common-mode rejection — is outside it, and attempting to model it in a functional testbench produces a slower simulation and no additional confidence. What is firmly inside the boundary is anything the electrical layer imposes back on the design, which by §6 means exactly one thing: the driver-enable timing. That is a legitimate and valuable assertion target once frame timing is defined, and the property to check is that the enable covers the entire frame including the final bit's full duration, with the margin on each side a parameter of the design rather than a constant.

Polarity and levels are integration checks, not functional ones. No amount of RTL verification detects a transceiver fitted on one side only. That class of defect is found by inspecting the board and by instrumenting the conductor, which is why §3's failure scenario is a bring-up procedure rather than a test case.

On an FPGA, the layer boundary is the I/O bank. The controller's pins are assigned an I/O standard and a bank voltage, and those must match what is actually connected — a mismatch is a constraint error that produces the deterministic corruption of §3, or damage. Two further practical points: an FPGA connected to an RS-485 transceiver must bring the enable out as a real pin and constrain it like any other output; and the overwhelmingly common FPGA arrangement is none of the three rows in Figure 2 but a fourth — a USB-to-serial bridge on the same board, presenting logic levels to the FPGA and a USB connection to a host. From the FPGA's side that is the direct logic-level case, which is why Chapter 1.5 treats it as the default debug arrangement rather than as a special one.

8. Understanding Check

9. Summary

A serial connection is a stack of independent decisions, and the UART controller occupies exactly one layer of it. Above are configuration choices; below the logic-level pins are the transceiver, the medium and the topology. The controller drives a level on a pin and has no representation of anything beneath it.

A transceiver translates the electrical representation of each bit while preserving the bit pattern, its order, each bit's duration and when a transmission begins. That is why the same controller works unchanged behind a direct connection, an RS-232 interface, or an RS-485 interface.

RS-232 is a physical-layer and interface standard: bipolar single-ended levels with a wide undefined band, inverted in polarity relative to logic level, defined for one device at each end. It is not a framing standard, and the merged phrase "UART is RS-232" causes real reasoning errors by attaching reach, voltages and topology to the wrong layer.

RS-485 is differential with a disableable driver, which makes it possible for many devices to share one pair. That makes multidrop electrically possible and supplies none of what a shared medium also needs — no addressing, no arbitration, no collision detection. Those come from a protocol layered on top, carried as ordinary UART bytes.

So topology is never a property of the framing. The question "can UART do multidrop" is malformed; the answerable questions are what the electrical layer permits and what higher-layer protocol organises it.

The electrical layer reaches back into the digital design in exactly one place: a half-duplex arrangement requires the design to produce a driver-enable, asserted before the first bit reaches the pin and held until the last bit has completed its full duration, resetting to disabled. That is a real design requirement, a legitimate assertion target, and the only part of the layer below that belongs inside a UART core's functional verification.

10. What Comes Next

The abstraction is now complete: what a UART is, where its timing comes from, what the link consists of, and what carries it. Chapter 1.5 puts the whole arrangement to work, walking the system architectures where UART actually appears — the boot console, the firmware log, the FPGA debug port, the board under bring-up — and asking what property of this design makes it the thing engineers still reach for. Chapter 1.6 then closes the module by comparing it against the alternatives an architect would weigh.

Browse the full path on the UART tutorials index. For a UART attached to a processor bus as an SoC peripheral — the layer above the controller, which this chapter treated only as "configuration" — see UART APB Interface.