Skip to content
VLSI Mentor

UART · Module 2

Clock Drift, ppm and Accumulated Timing Error

Where each endpoint's frequency error comes from, why only the relative error matters, and why two devices whose errors have opposite signs are the hard case. Displacement accumulates linearly in frame length, and that one fact explains most UART timing behaviour.

Chapter 2.3 left the receiver running open-loop: an origin acquired from one edge, every later position counted locally, no feedback and no refinement. The estimate can only degrade from the instant it is made.

This chapter measures how fast. It is the quantitative centre of the module, and it produces one relationship that explains most of what engineers observe about UART links — including why a link works on the bench and fails in the field, why lengthening a frame costs something real, and why "both ends are set to 115200" is not a statement about timing.

1. Where the Error Comes From

Three independent contributions make an endpoint's actual bit period differ from the nominal T_bit of Chapter 2.2.

The reference oscillator's accuracy. A crystal or oscillator module is specified within some tolerance of its nominal frequency, and the actual part sits somewhere inside that band. Which value it takes is fixed at manufacture and unknown to the design.

Environmental and ageing variation. The same part's frequency moves with temperature, and to a lesser extent with supply voltage and with age. A board that is correct at room temperature is not necessarily correct across its operating range, and this is the contribution that makes a link fail after deployment rather than on the bench.

The construction of the interval from that clock. Chapter 2.2 §6 established that F_clk / f_baud is essentially never a whole number, so the interval a design builds by counting whole cycles differs from the exact T_bit even with a perfect oscillator. This term is systematic — the same direction and magnitude on every interval — and it is entirely a design decision rather than a component property.

2. ppm, From First Principles

Frequency errors are small fractions, and expressing them as percentages produces inconvenient decimals. The conventional unit is parts per million:

Azvya Education Pvt. Ltd.VLSI Mentor
Snippet
1 ppm = 1 / 1,000,000 = 1 x 10^-6

so:

100 ppm = 100 / 1,000,000
        = 0.0001
        = 0.01 %

Applied to a real oscillator:

Azvya Education Pvt. Ltd.VLSI Mentor
Snippet
nominal    = 50 MHz = 50,000,000 Hz
error      = +100 ppm

Δf = 50,000,000 x (100 / 1,000,000)
   = 50,000,000 x 0.0001
   = 5,000 Hz

actual = 50,000,000 + 5,000
       = 50,005,000 Hz
       = 50.005 MHz
NominalErrorΔfActual
50 MHz+100 ppm5,000 Hz50.005000 MHz
100 MHz+50 ppm5,000 Hz100.005000 MHz
100 MHz+100 ppm10,000 Hz100.010000 MHz

Note the first two rows: the same absolute Δf of 5 kHz is 100 ppm at 50 MHz and 50 ppm at 100 MHz. ppm is a fraction, so it is the fractional form that transfers between frequencies, which is exactly why timing budgets are built from fractions rather than from hertz — the same reasoning Chapter 2.2 §2 applied to expressing displacement as a fraction of T_bit.

3. Two Endpoints, Two Errors

Define the quantities. For each endpoint, the fractional frequency error is how far its actual interval-generating rate sits from nominal:

Azvya Education Pvt. Ltd.VLSI Mentor
Snippet
ε_TX = (actual TX rate − nominal) / nominal        dimensionless
ε_RX = (actual RX rate − nominal) / nominal        dimensionless

Both are signed: positive means running fast, negative means running slow. Both fold in all three contributions of §1. And critically, neither endpoint knows either value — there is no measurement anywhere in the link (Chapter 2.1).

The actual bit periods that result are:

Azvya Education Pvt. Ltd.VLSI Mentor
Snippet
T_TX = T_bit / (1 + ε_TX)          the interval the transmitter really produces
T_RX = T_bit / (1 + ε_RX)          the interval the receiver really predicts

A faster rate gives a shorter interval, which is why the error appears in the denominator.

4. Only the Relative Error Matters

Here is the result that surprises engineers meeting this for the first time, and it is the most useful idea in the chapter.

The link does not care how far either endpoint is from nominal. It cares how far they are from each other.

The reason follows directly from Chapter 2.3: the receiver compares nothing against an absolute time reference. It acquires an origin from the transmitter's own signal and counts its own intervals forward. If both endpoints were 1% fast, the transmitter would produce intervals 1% shorter and the receiver would predict intervals 1% shorter, and the prediction would track the transmission perfectly. The frame would simply take slightly less time than nominal, and nothing would notice or care.

Define the quantity that does matter:

Azvya Education Pvt. Ltd.VLSI Mentor
Snippet
ε_rel  =  the fractional difference between the two intervals
       ≈  ε_TX − ε_RX          for |ε| much less than 1

The approximation is worth stating precisely rather than waving at. Exactly:

Azvya Education Pvt. Ltd.VLSI Mentor
Snippet
(T_RX − T_TX) / T_TX = (1 + ε_TX)/(1 + ε_RX) − 1
                     = (ε_TX − ε_RX) / (1 + ε_RX)

For the error magnitudes involved here — a few percent at worst, and usually far less — the denominator (1 + ε_RX) is within a few percent of one, so ε_TX − ε_RX is accurate to a few percent of an already small quantity. Every accumulation figure in this chapter uses the subtraction form and is labelled as such.

5. Accumulation Across a Frame

Now combine §4 with the open-loop prediction of Chapter 2.3.

The receiver predicts interval k's centre at (k + 0.5) of its own intervals from the origin. The transmitter places it at (k + 0.5) of its intervals. Each of the receiver's intervals is wrong by a fraction ε_rel of a bit period, and the errors share a sign — one endpoint is consistently the faster one — so they add rather than cancelling.

Under a deliberately simplified model — the origin is recorded exactly, the errors are constant across the frame, and nothing else contributes — the displacement after n intervals is:

Azvya Education Pvt. Ltd.VLSI Mentor
Snippet
Δt(n) ≈ n x ε_rel x T_bit

and as a fraction of a bit period, which is the form that transfers between rates:

Azvya Education Pvt. Ltd.VLSI Mentor
Snippet
Δt(n) / T_bit ≈ n x ε_rel

The relationship is linear in n. Doubling the frame length doubles the displacement at its end. That single fact is the reason Chapter 2.1 identified frame length as one of three quantities locked together, and the reason Chapter 2.2 insisted on carrying N_frame as a symbol.

Worked example

Stated fully, per the derivation discipline this module uses.

Azvya Education Pvt. Ltd.VLSI Mentor
Snippet
Known:
  f_baud = 115200 baud
  ε_rel  = 2%  = 0.02          ILLUSTRATIVE value, not a specification
  model  = simplified: exact origin, constant errors, no other terms

Bit period:
  T_bit = 1 / 115200
        ≈ 8.68056 µs

Displacement per interval:
  ε_rel x T_bit = 0.02 x 8.68056 µs
                ≈ 0.17361 µs     ( ≈ 173.6 ns )

After 8 intervals:
  Δt(8) ≈ 8 x 0.17361 µs
        ≈ 1.3889 µs

As a fraction of one bit period:
  1.3889 / 8.68056 ≈ 0.16

Interpretation:
  the receiver's predicted position for interval 8 sits about
  16% of a bit period away from where the transmitter actually
  placed it — having started, at interval 0, exactly aligned.

Across the frame, with the same assumptions:

Interval nΔt(n)as T_bitas % of a bit
1≈ 0.1736 µs0.02002.00%
4≈ 0.6944 µs0.08008.00%
8≈ 1.3889 µs0.160016.00%
9≈ 1.5625 µs0.180018.00%
10≈ 1.7361 µs0.200020.00%

Δt(n) ≈ n x ε_rel x T_bit — linear in the interval index

10 cycles
A serial line is shown over ten bit intervals of one frame. At interval zero the receiver's timing origin is established and the displacement between its predicted positions and the transmitter's actual positions is zero. Markers at intervals one, four, six and nine annotate the accumulated displacement as a fraction of a bit period, growing linearly from two percent at interval one to eighteen percent at interval nine under an illustrative relative error of two percent. A phase band marks the origin as the point of zero error and a second band covers the remainder of the frame where error grows without correction.origin — error is zeroorigin —error i…grows linearly, uncorrectedgrows linearly, uncorrectedk=1: 0.02 T_bit behindk=1: 0.02 T_bit behindk=4: 0.08 T_bit behindk=4: 0.08 T_bit behindk=6: 0.12 T_bit behindk=6: 0.12 T_bit behindk=9: 0.18 T_bit behindk=9: 0.18 T_bit behindlinet0t1t2t3t4t5t6t7t8t9
Figure 1 — displacement growing across one frame, at ε_rel = 2% (illustrative). Each column is one bit interval, not a system-clock cycle. The receiver's predicted position starts aligned at the origin and falls progressively further behind the transmitter's; the annotations are the computed values from the table above. Nothing corrects it during the frame, because nothing is measured after the opening edge.
A chain showing how timing displacement is produced. The transmitter's oscillator accuracy and its construction of the bit interval from its own clock combine into a single fractional error for the transmitter. The receiver's oscillator and its own interval construction combine into a fractional error for the receiver. Only the difference between those two totals, the relative error, affects the link, because the receiver measures itself against the transmitter's signal rather than against absolute time. That relative error is multiplied by the number of intervals elapsed since the frame's origin to give the accumulated displacement, and neither device measures any quantity in the chain.TX sideRX sideRelative errorInterval indexDisplacementoscillator +construction = ε_TXoscillator +construction = ε_RXε_rel ≈ ε_TX − ε_RXk intervals sincethe originΔt(k) ≈ k x ε_rel xT_bitnever measured byeither device
Figure 2 — how the three contributions of §1 combine into one displacement. Each endpoint's oscillator and its construction of the interval produce one fractional error; only the difference between the two endpoints' totals survives into the link, and that difference is multiplied by the interval index. Nothing in the chain is measured by either device.

6. The Structural Result

Set the accumulated displacement equal to half a bit period — the distance from a centre to a boundary — and solve for the interval count:

Azvya Education Pvt. Ltd.VLSI Mentor
Snippet
n x ε_rel = 0.5

n = 0.5 / ε_rel
ε_reln at half a bit
1.0%50.0 intervals
2.0%25.0 intervals
3.0%≈ 16.7 intervals
5.0%10.0 intervals

This is the relationship Chapter 2.1 promised, now in closed form: frame length and relative error trade against each other hyperbolically. Halving the tolerable error doubles the number of intervals a frame may contain, and vice versa. It also shows why asynchronous serial frames are short — at a few percent of mismatch, the usable run is a few tens of intervals, and a frame of ten sits comfortably inside that with room to spare.

7. What Resets, and What Does Not

The frame ends, the line returns to idle, and the next frame brings a new edge. It is worth being exact about what that changes, because the loose phrasing — "the drift resets" — is wrong in a way that matters.

The phase reference is re-established. The receiver acquires a new origin from the new edge, and the displacement accumulated during the previous frame is discarded along with the prediction that produced it. At interval 0 of the new frame, displacement is zero again.

The frequency errors are unchanged. ε_TX and ε_RX are properties of two oscillators and two designs. Nothing observed them, nothing adjusted them, and both endpoints continue at exactly the rates they were running at. They will produce the same accumulation, at the same rate, across the next frame and every frame after it.

So the sawtooth in Figure 1 repeats identically, frame after frame, forever. The mechanism does not reduce the error — it bounds the exposure, by ensuring no prediction is trusted for more than N_frame intervals. That is the fourth term of Chapter 2.1's bargain, now with the arithmetic behind it.

8. What This Means for Verification

This chapter converts vague timing anxiety into a small set of parameters, and that is exactly what a verification plan needs.

Nominal is the least interesting point. A testbench where both endpoints run at exactly the configured rate sets ε_rel = 0 and exercises none of this chapter. It will pass on a design with no margin whatsoever. Deliberate frequency error is the normal condition, not an error case.

The axis is ε_rel, and it is signed. Testing only ε_TX while leaving the receiver nominal explores half the space. The cases that matter are the opposite-sign pairings of §4, where two individually-compliant endpoints produce double the mismatch. A generator that picks ε_TX and ε_RX independently from their permitted ranges covers this naturally; one that varies a single combined knob does not distinguish (+1%, −1%) from (+2%, 0%), and while §4's algebra says they are nearly equivalent, a design that handles them differently has a bug worth finding.

Frame length is an independent axis, because §5 is linear in n. The longest supported configuration is the worst case by construction, so a plan that tests only the common arrangement leaves the actual boundary unexercised.

Boundary cases come in fours. Wherever the design's own budget predicts a failure point, a plan should place cases at nominal, comfortably inside, just inside, and just outside — and check that the outside case fails in the way the design claims it will, rather than merely failing. A formula predicting a boundary is an invitation to test both sides of it; §6's caution means the boundary to test is the design's computed budget, not this chapter's idealisation.

That is the beginning of the configuration space of Modules 14 and 15, and it has at least three dimensions before the frame's contents are considered at all.

9. What This Means on an FPGA

Two of the three contributions are yours. The far end's oscillator is fixed and unmeasurable. The fabric clock's accuracy is a board decision. But the construction error — the fractional part discarded in Chapter 2.2 §6 — is entirely a design choice, and it is the term an engineer can actually reduce. Chapter 4.4 covers doing so.

The construction term can dominate. With a high ratio of clock to rate, the fractional part is a small share of an interval and the crystals dominate. Push the serial rate up, or the fabric clock down, and the ratio shrinks, the discarded fraction becomes a larger share, and the design's own arithmetic becomes the main contributor. That crossover is worth computing rather than assuming.

Budget across temperature, not at the bench. §1's environmental term is what turns a working prototype into a field failure, and the bench is the one place it is smallest.

And the far end may not be a crystal at all. A USB-to-serial bridge, a host's peripheral, or another FPGA each derive their rate differently and with different accuracy. The safe posture is to budget for the range the far end is specified over, not for what a particular unit happens to measure.

10. Understanding Check

11. Summary

An endpoint's bit period differs from nominal for three reasons: its oscillator's accuracy, environmental and ageing variation, and its construction of the interval from a clock that does not divide evenly. The first two are component properties; the third is a design decision, and it is systematic rather than random.

ppm is the conventional unit — 100 ppm is 10^-4, or 0.01%, so a 50 MHz part at +100 ppm runs at 50.005 MHz. Because ppm is a fraction, it is the fractional form that transfers between frequencies.

The link is insensitive to how far either endpoint is from nominal, because the receiver measures itself against the transmitter's signal rather than against absolute time. What matters is ε_rel ≈ ε_TX − ε_RX — and the consequence is that opposite signs are the hard case: two endpoints each individually within 1% can be 2% apart, since a tolerance bounds distance from nominal and two independent draws can land at opposite extremes.

Displacement accumulates because the receiver runs open-loop and the per-interval errors share a sign:

Azvya Education Pvt. Ltd.VLSI Mentor
Snippet
Δt(n) ≈ n x ε_rel x T_bit

Linear in the interval index. At 115200 baud with an illustrative 2% relative error, that is about 173.6 ns per interval and roughly 1.39 µs — about 16% of a bit period — by interval 8.

Setting the displacement to half a bit gives n = 0.5 / ε_rel, the hyperbolic trade between frame length and mismatch that explains why asynchronous serial frames are short. It is an idealisation, not a tolerance figure: it assumes an exact origin, a full half-bit of usable margin, and no other contributions, and none of those holds in a real design.

At the next frame the phase reference is re-established and displacement returns to zero. The frequency errors are not changed — nothing measured or adjusted them — so the same accumulation repeats identically in every frame. The mechanism bounds exposure rather than reducing error.

12. What Comes Next

This chapter produced a displacement and deliberately declined to say whether it is survivable. Chapter 2.5 answers that, and closes the module: why the centre of an interval is the position worth aiming at, how much of the bit period is genuinely available as margin, which terms besides this chapter's drift compete for it, and — the misconception this module has been building toward correcting — exactly what the end of a frame does and does not restore.

Browse the full path on the UART tutorials index. For accumulated timing error in a clocked interface, where the equivalent budget is closed by periodic re-training rather than by ending a frame, see Write Levelling.

Continue learning

Where this fits

Part of the UART curriculum.