CPHA — Clock Phase

Chapter 3.1 named the first configuration bit: CPOL fixes the level SCLK rests at, and therefore the direction of the leading edge. It deliberately said nothing about what either edge does.

This chapter names the second bit, and with it the module has everything it needs.

Which of the two logical edges carries the sample role — and why is that choice independent of polarity?

The independence is the part worth working for. Two independent binary choices give four combinations, and those four combinations are the SPI modes. If the bits were entangled — if polarity somehow constrained phase — there would be fewer than four, and the modes would have to be memorised as special cases rather than derived. Chapter 3.3 does the deriving; this chapter establishes that there is something to derive.

1. CPHA Assigns the Roles

Chapter 2.3 established the contract: within each bit time, one edge launches a new bit onto the line and the other samples whatever the line is carrying, and they must be different edges. It named the two edges using Chapter 2.2's position-based vocabulary — leading and trailing — and left the assignment open.

CPHA — clock phase — closes it.

CPHA = 0 means the leading edge samples, so the trailing edge launches. CPHA = 1 means the trailing edge samples, so the leading edge launches.

That is the whole definition. Three things follow directly, and each matters later.

One bit fixes both roles. Because launch and sample are complementary — Chapter 2.3 built them as complementary selections precisely so they could never coincide — naming the sampling edge names the launching edge too. There is no separate "launch phase" configuration, and a device that specified one independently would be describing something other than SPI.

It is stated in logical terms, so it is polarity-independent. CPHA says leading or trailing, not rising or falling. Whether the leading edge happens to be rising is CPOL's business. This is exactly why Chapter 2.2 insisted on the position-based vocabulary: without it, CPHA could not be defined without also mentioning polarity, and the two bits would not be separable.

Both directions follow it. The master launching on MOSI and the slave launching on MISO use the same edge; the master sampling MISO and the slave sampling MOSI use the other. One bit governs all four events, because Chapter 1.3's ring shifts once per bit time at each end.

2. The Same Clock, Two Different Transfers

Read the two data rows against the same clock.

The cpha = 0 row changes on trailing edges. Its bit boundaries sit at columns 3, 5 and 7 — the falling edges — and the receiver reads it at columns 2, 4 and 6, the rising edges. Each bit is therefore sampled at the start of its bit time.

The cpha = 1 row changes on leading edges. Its bit boundaries sit at columns 2, 4 and 6, and the receiver reads at columns 3, 5 and 7. Each bit is sampled in the middle of its bit time, half a period after being launched.

The first bit is where they genuinely differ. Look at column 1, before any clock edge has occurred. The cpha = 1 row is still undefined — nothing has been launched, because the launching edge has not arrived. The cpha = 0 row already carries b2, because its first sampling edge is the very first edge of the transfer, and something has to be there to sample.

That asymmetry is not cosmetic. It is the hardest implementation consequence in this module, and §4 works through it.

3. Why the Two Bits Are Independent

It is worth proving the independence rather than asserting it, because the whole four-mode structure rests on it.

CPOL is a statement about the line's level when idle. CPHA is a statement about which position within the bit time carries the sample role. Neither statement mentions the other's subject matter, and there is no combination of the two that is contradictory or meaningless:

• Clock idles low, leading edge samples — coherent.
• Clock idles low, trailing edge samples — coherent.
• Clock idles high, leading edge samples — coherent.
• Clock idles high, trailing edge samples — coherent.

All four describe a working transfer. None of them collapses into another. So the configuration space really is two independent bits, and it really does have exactly four members.

The reason this feels less obvious than it is comes from the physical view. If you insist on describing everything in rising/falling terms, the two bits appear to interact: with CPOL = 0, CPHA = 0 the sampling edge is rising, and with CPOL = 1, CPHA = 0 it is falling. Same CPHA, different physical edge — which looks like interference.

It is not. CPHA held its meaning perfectly: the leading edge samples, in both cases. What changed was which physical direction the leading edge points, which is CPOL's job. The apparent entanglement is an artefact of using the wrong vocabulary, and it dissolves the moment you describe the transfer in leading/trailing terms. This is Chapter 2.2's argument arriving at its destination.

4. The First-Bit Problem

CPHA = 0 creates a genuine implementation difficulty that CPHA = 1 does not, and it is worth stating precisely because it shapes both master and slave design.

With CPHA = 0, the first sampling edge is the first edge of the transfer. A receiver reads the line at that instant, so a transmitter must already have placed a valid bit there. But the transmitter cannot have used a clock edge to do it — there has not been one yet.

So the first bit has to be launched by something else, and in practice that something is the assertion of chip select. The falling edge of CS, which Chapter 1.2 established as the event that prepares a device to participate, doubles as the launch event for bit one. Every subsequent bit launches on a trailing edge as normal.

Three consequences follow.

The transmitter has a special case. Its datapath cannot simply be "launch on the configured edge" — it must also launch on CS assertion when CPHA = 0. That is an extra path into the shift register's output, and it is the part of a slave design that most often goes wrong. Chapter 3.4 implements it.

The CS lead interval acquires a second obligation. Chapter 2.5 required enough time after CS for the device's internal preparation. With CPHA = 0 it must also be long enough for the device's CS-to-output-valid time — the parameter Chapter 2.6 §5 introduced — because the first bit must be not merely launched but settled before the first clock edge samples it.

CPHA = 1 has no such problem. Its first launching edge is the first edge of the transfer, and its first sampling edge is the second. Everything is uniform: every bit is launched on a leading edge and sampled on a trailing one, with no exception for the first. This makes CPHA = 1 measurably easier to implement correctly, particularly in a slave, and it is a legitimate reason to prefer it when a device offers a choice.

5. Why This Chapter Has No New RTL

Deliberate, and the reason is architectural rather than editorial.

CPHA's entire hardware effect is to choose which of two strobes plays which role — and that module already exists. Chapter 2.3 built spi_edge_roles, which takes exactly two configuration inputs and produces the launch and sample strobes:

idle_high           ← this is CPOL   (Chapter 3.1 gave it a name)
sample_on_trailing  ← this is CPHA   (this chapter gives it a name)

The module was written against the logical vocabulary before either bit had a standard name, so naming them requires no code change at all. Writing a new module here would duplicate roughly ten lines to rename two ports — exactly the code inflation this curriculum avoids.

What is new is hardware, and it belongs to CPHA = 0 rather than to CPHA in general: the first-bit launch path of §4. That is genuinely new logic, it is not a rename of anything, and Chapter 3.4 builds it in all three HDLs where the reader has the context to understand why it exists.

The correct representation for this chapter is the waveform of §2 and the independence argument of §3 — the conceptual groundwork that makes Chapter 3.3's derivation and Chapter 3.4's RTL make sense.

6. Why a Verification Engineer Cares

CPHA changes one line in a monitor and one entry in a configuration object, and getting either wrong produces wrong transactions from a correct DUT.

Sample where the receiver samples. Chapter 1.4's monitor fragment sampled on posedge sclk and was explicitly flagged as a placeholder. The real answer is now complete: derive the logical leading edge from cpol, then choose leading or trailing according to cpha. That is the same two-step mapping the RTL performs, and a monitor that implements it works against every mode rather than one.

Both bits belong in configuration, together. They are properties of the attached device, read from its datasheet. Carrying them as a single two-bit mode field is the conventional form, and Chapter 3.3 shows the encoding. A monitor that hard-codes either bit is single-use, the same argument made for the resting level in Chapter 2.2 and the CS intervals in Chapter 2.5.

CPHA = 0 needs a checker the other mode does not. Because the first bit is launched by CS rather than by a clock edge, a monitor must know to capture it from a different event, and a checker can usefully assert that the line is not unknown at the first sampling edge. That single assertion catches a transmitter that forgot the special case — a bug which otherwise shows up only as a corrupted first bit that looks like a dozen other faults. Chapter 3.4 writes it.

7. Why an FPGA or ASIC Engineer Cares

CPHA = 0 is the harder case to implement, especially as a slave. The first bit must be driven from the CS edge, which for an FPGA slave means a path from an asynchronous input pin to the MISO output that does not pass through the normal clocked datapath. That is an awkward path to constrain and an awkward one to close, and it interacts with the clock-domain question Module 15 owns. A design that supports only CPHA = 1 is meaningfully simpler — which is a legitimate scoping decision if the devices you must talk to allow it, and a trap if they do not.

As a master, the difficulty is smaller but real. The master owns the clock and CS, so it can sequence the first launch deterministically. It still needs the extra launch path, and it must ensure the first bit is driven early enough within the CS lead interval to satisfy the device's setup requirement before the first edge.

Changing CPHA does not move any edge. Unlike a clock-rate change, switching phase alters which edge the datapath acts on, not the clock's shape. No I/O timing constraint changes, no path lengths change. What changes is which half of the bit time the data is stable in — relevant to the round-trip budget only insofar as it determines where the sampling instant sits.

8. Failure Signature — The First Bit Is Wrong, Everything Else Is Right

Symptom. Received words are consistently wrong in exactly one position: the most significant bit is incorrect, or appears to be a repeat of something, while the remaining bits are exactly as expected. Completely reproducible, at every clock rate.

Plausible mechanisms. A transmitter that does not implement the CPHA = 0 first-bit launch is the leading candidate — it waits for a clock edge that, for bit one, never comes before the sample. Competing explanations are a CS lead interval too short for the device's CS-to-output-valid time, so the first bit is launched but not settled; and a full mode mismatch, which would displace every bit rather than one.

The discriminating observations. First, is it exactly one bit? A mode mismatch shifts the whole word (Chapter 3.8); a first-bit fault leaves bits two onward correct. That distinction is visible in the data alone and eliminates half the hypothesis space.

Second, is the configuration CPHA = 0? If the link is running CPHA = 1, the first-bit path does not exist as a special case and this mechanism is ruled out entirely.

Third, scope the line between CS assertion and the first clock edge. If it is undefined or still transitioning there, the first bit was never launched or was launched too late. If it is settled and correct, the transmitter is fine and the receiver's first sampling edge is landing somewhere unexpected — which points back at CS timing.

Why reproducibility matters here. A missing first-bit launch is a structural omission, so it fails identically every time. If the first bit is intermittently wrong, the launch path exists but the CS lead interval is marginal against the device's CS-to-output-valid time — a timing problem with a different fix.

9. Common Misconceptions

10. Reason It Through

Work this before reading the answers.

You are specifying an FPGA that must act as an SPI slave to an existing host processor. The host's driver is fixed and configurable for any mode. A colleague argues the FPGA should support all four modes "for flexibility." Another argues for supporting only CPHA = 1 and requiring the host to be configured accordingly. Evaluate.

What is actually being traded? Implementation complexity against integration freedom. The two CPHA values are not equal work: CPHA = 1 launches every bit, including the first, on a leading edge, so the datapath is uniform. CPHA = 0 additionally requires the first bit to be driven from the CS assertion, which in an FPGA slave is a path from an asynchronous input pin to an output — not through the regular clocked datapath, and awkward to constrain and close.

Does supporting only CPHA = 1 actually work here? Yes, given the stated premise that the host's driver is configurable. Mode is a host-side setting, the host is fixed but configurable, and one line of initialisation selects it. That premise is what makes the narrow option viable, and it is the first thing to verify rather than assume.

What makes the flexible option more expensive than it looks? Not just the extra launch path. It also doubles the mode space the FPGA must be verified across — all four combinations rather than two — and the first-bit path is precisely the one most likely to harbour a bug, because it is exercised once per transaction and only in half the configurations. Coverage of it is easy to omit and easy to fool.

What is the risk of the narrow option? It is a constraint on the system, recorded somewhere other than the FPGA. If the host is later replaced, or a second master is added, or a bootloader configures SPI before the driver runs and picks a different mode, the FPGA silently stops working in a way nobody associates with the FPGA. The mitigation is to make the constraint loud: document it in the interface specification, and — better — have the slave detect a mode it cannot serve rather than misbehave. A slave that can observe the polarity of its idle clock can at least flag a mismatch.

What would you actually recommend? Support CPHA = 1 only if the constraint can be recorded and enforced at the system level, because the implementation and verification savings are real and the first-bit path is a genuine defect magnet. Support both if the FPGA is a product others will integrate, where you cannot control the host. The decision is about who owns the integration, not about which is technically nicer — and stating it that way is what makes it a design-review answer rather than a preference.

11. Understanding Check

12. Summary

CPHA specifies which logical edge carries the sample role. CPHA = 0: the leading edge samples and the trailing edge launches. CPHA = 1: the trailing edge samples and the leading edge launches. One bit fixes both roles, because launch and sample are complementary by construction, and it governs both directions because Chapter 1.3's ring shifts once per bit time at each end.

It is stated in logical terms — leading and trailing — which is what makes it independent of CPOL. Describe the same transfer physically and the two bits appear to interact; describe it in Chapter 2.2's vocabulary and the independence is immediate. All four combinations are coherent and distinct, which is why the configuration space has exactly four members and why they can be derived rather than memorised.

The two values are not equally easy to implement. CPHA = 0 samples on the very first edge of the transfer, so the first bit must already be present — launched by the assertion of CS rather than by any clock edge. That adds a datapath, adds a requirement on the CS lead interval to cover the device's CS-to-output-valid time, and in an FPGA slave creates an awkward path from an asynchronous pin to an output. CPHA = 1 is uniform for every bit, including the first.

No new RTL was needed here: Chapter 2.3's role mapper already implements both bits, having been written against the logical vocabulary before either had a name. The genuinely new hardware belongs to CPHA = 0 alone and is built next.

13. What Comes Next

Both bits are now named. Chapter 3.3 — Deriving Mode Behaviour from CPOL and CPHA combines them: the standard mode numbering, the derivation you can perform from first principles in a few seconds, the complete decoder in three HDLs, and the assertion that keeps a mode-configurable design honest. After that, Chapters 3.4 to 3.7 walk each combination in working depth — starting with the one that carries the first-bit problem.

Browse the path on the SPI curriculum index, or revisit CPOL — Clock Polarity for the first bit, or Launch and Sample Edges for the contract this chapter configures.