Leading and Trailing Edges

Chapter 2.1 produced a clock and a period. Before anything can be said about what the clock does, there is a vocabulary problem to clear up — and it is not pedantry. It is the reason two engineers can read the same datasheet sentence, implement it correctly by their own lights, and end up with a link that does not work.

Why are "rising" and "falling" insufficient descriptions of an SPI transfer?

The short answer: because SPI does not fix the level the clock rests at between transfers. Once that level is configurable, "the rising edge" stops identifying a position in the transfer and starts identifying a direction of voltage change — and those are only the same thing for half of the possible configurations.

This chapter is short on mechanism and long on precision. That is appropriate: it exists to install two words that the rest of the module, and all of Module 3, are written in.

1. The Clock Rests Somewhere

Between transfers, SCLK is not toggling. Chapter 2.1's divider parked it when the enable dropped, and Chapter 1.2 established that the master owns the line the whole time — it is being held, not abandoned.

At what level? SPI does not say. Some devices expect the clock to rest low and rise to begin activity; others expect it to rest high and fall to begin activity. Both arrangements are ordinary, both appear across common parts, and a master is configured to match whichever the device requires.

That configuration bit has a name, and naming it here would start a chapter that belongs elsewhere: Module 3 introduces it, derives its consequences, and combines it with a second bit to produce the four SPI modes. What Module 2 needs is only the fact that the idle level varies, because that fact breaks a piece of vocabulary everyone arrives with.

2. Why "Rising Edge" Stops Meaning Anything

Consider a datasheet sentence that appears, in some form, in a great many device specifications:

Data is sampled on the leading edge of SCLK.

Now consider the sentence an engineer often writes in a design note instead:

Data is sampled on the rising edge of SCLK.

For a device whose clock idles low, those sentences describe the same event. The clock rests at 0, the first thing it does is rise, and that rising edge is the first edge of the transfer.

For a device whose clock idles high, they describe opposite events. The clock rests at 1, the first thing it does is fall, and that falling edge is the first edge of the transfer. The first rising edge now occurs half a period later — in the middle of the first bit time, not at its start.

So "rising" and "falling" describe the direction a voltage moves. "Leading" and "trailing" describe position within the transfer. Only the second pair survives a change of idle level, which is exactly why specifications are written in it.

3. The Definitions

State them precisely, because the rest of the module uses them constantly.

The leading edge of a bit time is the first SCLK edge of that bit time — the transition that takes the clock away from its resting level.

The trailing edge is the second edge of the bit time — the transition that returns the clock to its resting level.

Three properties follow immediately, and each one matters later.

Every bit time has exactly one of each. One period, two edges, in a fixed order: leading then trailing. That is what makes the pair a usable coordinate system for describing where in a bit time something happens.

Their physical direction depends on the idle level, and nothing else. Idling low: leading is rising, trailing is falling. Idling high: leading is falling, trailing is rising. There is no third case.

Their position in time does not depend on the idle level. The leading edge occurs at the start of the bit time either way. This is the property that makes the vocabulary portable, and it is the reason a device can specify its behaviour once rather than twice.

Read the figure by comparing columns rather than shapes. At column 2 both traces have an edge: the upper one rises, the lower one falls. Both are leading edges, both start bit b2, and both are the moment a device specified "on the leading edge" would act. An implementation that hard-coded "rising" would act at column 2 on the upper trace and at column 3 on the lower — half a bit time late, every bit, for the whole transfer.

4. Why the Distinction Has Teeth

It would be a harmless naming convention if the two vocabularies disagreed only in words. They disagree in time, and the size of the disagreement is exactly half a bit time.

That is the worst possible size. A whole-bit-time error would be obvious: data would be offset by a full bit and nothing would work in a way anyone could miss. A half-bit-time error moves the moment of action from the start of a bit time to its middle — which, depending on which other configuration choices were made, produces one of three outcomes:

• it works anyway, because the moved edge happens to land somewhere the data is still valid, and the bug survives bring-up to be discovered later on a different board or at a different frequency;
• it captures the wrong bit, producing the one-position offset Chapter 1.3 taught you to recognise as a position error rather than a data error;
• it captures while the line is changing, producing intermittent, data-dependent corruption that looks electrical and is not.

All three are common. The first is the most dangerous, because it converts a specification misreading into a latent fault.

5. Reading a Capture: Translating Back

In the lab the translation runs the other way, and it is worth being deliberate about it because instruments speak the electrical vocabulary.

A logic analyser or oscilloscope shows you voltage against time. It knows nothing about idle levels or leading edges; it shows a rising edge and a falling edge. To convert that into protocol terms you need one additional fact, and it is visible in the same capture:

Look at SCLK while CS is deasserted. That is the resting level, by definition — Chapter 2.1's parked clock. Read it off the trace before the transfer begins.

From there the mapping is mechanical. If the clock rests low, every rising edge in the transfer is a leading edge and every falling edge is a trailing edge. If it rests high, the mapping is reversed. Once you have it, a device's datasheet sentence — "data is sampled on the leading edge" — becomes an instruction about a specific, identifiable edge in the capture in front of you.

This is the first genuinely transferable debugging habit in the timing module: establish the resting level before interpreting a single edge. An engineer who skips it and assumes "rising is leading" will misread half the captures they ever see, and the misreadings will be the confusing ones, because they occur on exactly the devices whose configuration is unfamiliar.

6. Why an RTL Designer Cares

There is no RTL in this chapter — the concept is naming, not hardware — but the naming has a direct structural consequence that Chapter 2.3 then builds.

A master that supports both resting levels does not contain two datapaths. It contains one, driven by two strobes — a leading-edge strobe and a trailing-edge strobe — and a small piece of configuration deciding which physical SCLK transition generates each. Chapter 2.1's divider already produces the raw material: sclk_rise and sclk_fall, one pulse each per period. Mapping those two physical pulses onto the two logical roles is a two-input multiplexer, not a duplicated design.

That is the whole architectural payoff of getting the vocabulary right. Design the shift logic against leading and trailing and the configuration collapses into a mux at the edge of the module. Design it against rising and falling and the configuration leaks into the datapath, where it multiplies.

7. Why a Verification Engineer Cares

The same discipline determines whether a monitor is reusable.

Sample on a logical edge, not a physical one. A monitor written to sample MOSI on posedge sclk works for exactly one resting level. The same monitor written to sample on a leading edge — derived once from the configured resting level — works for both, and it is the same amount of code. Which of the two you write decides whether your SPI agent survives its second project.

The resting level belongs in the configuration object. It is not something a monitor should infer per transfer, because inferring it requires seeing an idle period and a transfer that may not have happened yet. It is a property of the link, known before the test starts, and it belongs alongside the transfer width and bit order that Chapter 1.4's transaction modelling needed. Module 16 assembles that configuration properly.

A checker can verify the resting level itself. "SCLK is at its configured idle level whenever CS is deasserted" is a genuine, cheap invariant, and violating it means a master is leaving the clock somewhere a device may not tolerate — or that the configuration and the hardware disagree. It is one of the few things about this chapter that is directly assertable, and Chapter 2.5 states it formally once CS timing is on the table.

8. Failure Signature — Everything Off by Half a Bit Time

Symptom. A link to a new device returns data that is wrong in a structured way: every received word looks like a neighbouring bit pattern rather than random garbage, and the transmitted data is accepted correctly, or vice versa. The failure is completely reproducible — the same wrong value every time.

Candidate mechanisms. A half-bit-time displacement has a small number of causes. The master's configured resting level does not match the device's requirement, so the master's "first edge" is the device's mid-bit. The implementation hard-coded a physical edge direction where the device specifies a logical one. Or the edge role assignment is inverted — a distinct configuration that Chapter 2.3 introduces and Module 3 combines with this one.

The discriminating observation. Capture SCLK with CS visible and read the level while CS is deasserted. Compare it against what the datasheet says the device requires at rest. If they disagree, you have found it — the master is configured for the wrong resting level and every edge in the transfer is playing the wrong role. If they agree, the resting level is correct and the fault is in the edge-role assignment instead, which is the next chapter's territory.

Why reproducibility is the clue. A configuration error is deterministic: same inputs, same wrong output, every time, at every frequency. Timing-margin failures (Chapter 2.4) and round-trip shortfalls (Chapter 2.7) are frequency-dependent and intermittent. So the first question in a timing investigation is not "what is wrong" but "is it reproducible" — and a perfectly reproducible timing symptom points at configuration rather than at margin.

9. Common Misconceptions

10. Reason It Through

Work this before reading the answers.

An engineer ports working SPI firmware from one board to another. The controller is the same, the driver is the same, and the new peripheral is from a different vendor. Every read returns a value that is exactly the expected value shifted one position, identically on every attempt. The engineer's first move is to try the other bit-order setting.

Is bit order a reasonable first hypothesis? It is a reasonable hypothesis and a poor first move, because it is cheap to try and therefore tempting to try before thinking. Chapter 1.3 drew the distinction that settles it: a bit-order mismatch produces a word that is bit-reversed, while a timing displacement produces a word that is shifted by one position. Those are different patterns, and the symptom here is stated as a shift. Comparing the received value against both candidate patterns — the reversal and the shift — costs nothing and eliminates one hypothesis immediately.

Given a shift, what are the candidates? A half-bit-time displacement of the sampling moment, which has two configuration causes: the resting level does not match what the new device expects, or the edge-role assignment does not. Both produce a consistent one-position offset, and neither is distinguishable from the other by looking at the received data alone.

What is the decisive measurement? Capture SCLK together with CS. Read the SCLK level while CS is deasserted and compare it against the new device's datasheet. This is a single observation and it partitions the problem: a mismatch here is the answer; a match rules out the resting level entirely and leaves the edge-role assignment as the remaining cause.

Why did porting expose it? Because the previous device's requirements were baked into firmware that was written against that device, quite possibly using physical edge language rather than logical. Vendors differ in which resting level they expect, and a driver that hard-codes "rising" rather than deriving it from configuration carries a hidden dependency on the old part. This is the practical argument for §6's structural point: express the design against leading and trailing, and the port becomes a configuration change rather than a debugging session.

What would make the reproducibility mislead you? Nothing about it should — but it is worth stating the inverse. If the same port had produced intermittent corruption instead, the resting level would be an unlikely culprit and the investigation should move to margin and the round trip. Reproducible means configuration; intermittent means timing. That heuristic is worth more in practice than any individual fix.

11. Understanding Check

12. Summary

SPI does not fix the level SCLK rests at between transfers. Some devices expect it to rest low, some high, and a master is configured to match. That single variability breaks the vocabulary most engineers arrive with.

Rising and falling name a direction of voltage change. They are what an instrument shows and what an electrical description needs. Leading and trailing name a position within the bit time: the leading edge is the first edge, taking the clock away from rest; the trailing edge is the second, returning it. Only the second pair is portable, which is why device specifications are written in it.

The two vocabularies coincide when the clock rests low and invert when it rests high, and the disagreement is exactly half a bit time — the worst possible size, because the displaced moment often still lands inside a valid data window. A configuration error of this kind therefore frequently produces a working link, and surfaces later as a mysterious failure on a board with less margin.

Two habits follow. In the lab, establish the resting level first, by reading SCLK while CS is deasserted, before interpreting any edge. In design and verification, express everything against the logical edges, so that supporting both resting levels is a mux and a configuration field rather than a duplicated datapath or a second monitor.

13. What Comes Next

You now have a coordinate system for a bit time. Chapter 2.3 — Launch and Sample Edges puts it to work by assigning the two edges their jobs: one of them places a new bit on the wire, the other captures the bit that is there, and they must be different edges for reasons this chapter's figure makes almost obvious. That separation is the contract the whole protocol rests on, and it is where the half-period of Chapter 2.1 becomes the budget that Chapter 2.4 starts spending.

Browse the path on the SPI curriculum index, or revisit SCLK Generation, Period, and Frequency for the parked clock whose level this chapter interprets.