SPI — Tutorials · VLSI Mentor

129Total chapters

20Modules

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20 / 20Active modules

Modes you derive, not memorise

The full-duplex shift-register model and the launch/sample clocking contract come first — so Modes 0–3 are derived from CPOL and CPHA rather than recited from a table.

Built for RTL, DV and FPGA work

Master and slave RTL as flagship modules, plus SPI clock domains, synchronizers, and the input/output delay constraints that decide whether a slave closes timing.

Design → verify → debug

Verification planning through monitors, scoreboards, SVA, coverage and a UVM agent — then a systematic waveform-debug method, and a design-and-verify capstone.

SPI Complete Curriculum

Your Learning Roadmap

129 chapters · 20 modules — full-duplex shift-register transfers, derived CPOL/CPHA modes, master and slave RTL, and SPI clock domains.

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Module 1

SPI Architecture and Mental Model

1.1Why SPI Exists 1.2Master, Slave, and Signal Ownership 1.3The Shift-Register Mental Model 1.4Full-Duplex Exchange 1.5Bus Topologies and Daisy-Chain 1.6Electrical and Board-Level Limits

Module 2

SPI Timing Fundamentals

2.1SCLK Generation, Period, and Frequency 2.2Leading and Trailing Edges 2.3Launch and Sample Edges 2.4Setup, Hold, and Timing Margin 2.5CS-to-SCLK and SCLK-to-CS Timing 2.6Slave Output Valid Timing 2.7Master Input Capture and Round-Trip Delay

Module 3

CPOL, CPHA, and the Four SPI Modes

3.1CPOL — Clock Polarity 3.2CPHA — Clock Phase 3.3Deriving Mode Behaviour from CPOL and CPHA 3.4Mode 0 (CPOL=0, CPHA=0)3.5Mode 1 (CPOL=0, CPHA=1)3.6Mode 2 (CPOL=1, CPHA=0)3.7Mode 3 (CPOL=1, CPHA=1)3.8Mode Mismatch and Its Failure Signature

Module 4

SPI Framing

4.1Why SPI Has No Universal Frame Format 4.2Transfer Width 4.3Bit Ordering — MSB-First and LSB-First 4.4Command, Address, and Data Phases 4.5Dummy Phases and Read Latency

Module 5

SPI Write Transactions

5.1Anatomy of a Write Transaction 5.2MOSI Data Flow and CS Framing 5.3Register and Multi-Byte Writes 5.4Write Waveform Analysis

Module 6

SPI Read Transactions and Latency

6.1Anatomy of a Read Transaction 6.2Command-Then-Read Sequences 6.3MISO Valid Timing 6.4Read Latency Accounting 6.5Read Waveform Analysis

Module 7

Multi-Byte, Burst, and Continuous Transfers

7.1Continuous Transfers Under One CS 7.2Burst Transfers and Auto-Increment 7.3Back-to-Back Transactions and Inter-Frame Gap

Module 8

Bus Ownership and Multi-Slave Systems

8.1Chip Select Semantics and Device Selection 8.2Shared MOSI, Shared MISO, Individual CS 8.3Slave Output Enable and MISO Tri-State 8.4Bus Turnaround and the Contention Window 8.5MISO Contention and Multiple Slaves Selected 8.6CS Glitches and False Selection 8.7Partial and Aborted Transactions

Module 9

SPI Performance

9.1Raw vs Effective Payload Throughput 9.2Protocol Overhead 9.3Burst Efficiency and Transfer Sizing 9.4Maximum Practical SCLK

Module 10

Real Devices and Datasheet Interpretation

10.1How to Read an SPI Device Datasheet 10.2Identifying the Required SPI Mode 10.3Extracting Setup, Hold, and Maximum SCLK 10.4Command Encoding and Register Access 10.5Address Fields, Dummy Cycles, and Burst Behaviour 10.6From Datasheet to Transaction Specification

Module 11

SPI Flash and Boot

11.1Serial Flash Architecture 11.2Normal Read, Fast Read, and Dummy Cycles 11.3Page Program, Page Boundaries, and Erase 11.4Status Registers, WIP/WEL, and Polling 11.5Boot from SPI Flash 11.6FPGA Configuration over SPI 11.7Boot and Flash Transaction Analysis

Module 12

Dual, Quad, Octal SPI, and XIP

12.1Why Wider SPI Exists 12.2Dual, Quad, and Octal SPI 12.3Lane Widths per Phase and Direction Changes 12.4SDR, DDR Transfers, and Throughput 12.5XIP and Memory-Mapped Controllers

Module 13

Designing an SPI Master in RTL

13.1From Protocol to Design Requirements 13.2Master Microarchitecture 13.3The Master Control FSM 13.4Clock Divider and SCLK Generation 13.5CPOL/CPHA-Aware Edge Control 13.6TX and RX Shift Registers 13.7Chip-Select Generation 13.8Configurable Transfer Width and Bit Order 13.9Multi-Byte and Back-to-Back Transactions 13.10Busy/Done/Valid Interface, Reset, and Abort 13.11Synthesizable Master Architecture and RTL Review

Module 14

Designing an SPI Slave in RTL

14.1Slave Microarchitecture and Clocking Assumptions 14.2CS Detection and Transaction Boundaries 14.3MOSI Capture and Bit Counting 14.4MISO Generation and Launch Timing 14.5MISO Output Enable and Release 14.6CPOL/CPHA Handling in a Slave 14.7Transfer Width, Partial Frames, and Aborts 14.8Reset Behaviour and Safe Idle 14.9The System-Side Interface 14.10Synthesizable Slave Architecture and RTL Review

Module 15

SPI Clock Domains and FPGA Timing

15.1Why an SPI Slave Is a Clock-Domain Problem 15.2Architecture A — SCLK as a Clock Domain 15.3Architecture B — Oversampling SCLK 15.4Choosing an Architecture 15.5Synchronizers and Their Limits 15.6Handshake and FIFO Crossings 15.7Input and Output Delay Constraints 15.8FPGA I/O Registers and Timing Closure 15.9CDC and Constraint Failure Modes

Module 16

SPI Verification Fundamentals

16.1Extracting Protocol Rules and the Verification Plan 16.2Transaction Modelling and Stimulus 16.3The SPI Interface and Clocking Blocks 16.4Driver Architecture 16.5Monitor and Transaction Reconstruction 16.6Reference Model and Scoreboard 16.7Active and Passive Agents

Module 17

SPI Assertions, Coverage, and UVM

17.1SPI Protocol Assertions 17.2Mode-Aware Checking and Assertion Pitfalls 17.3Functional Coverage and Meaningful Crosses 17.4Constrained-Random Sequences 17.5A Reusable UVM SPI Agent 17.6Corner Cases That Break SPI Designs 17.7Verification Closure

Module 18

SPI Debugging and Waveform Reasoning

18.1A Systematic Waveform Debug Method 18.2Wrong CPOL, Wrong CPHA, Wrong Sampling Edge 18.3Bit Shifts, Bit-Order Mismatch, and Clock-Count Errors 18.4Transfer-Width and Dummy-Cycle Errors 18.5CS Timing Faults and Partial Frames 18.6Read Corruption and MISO Contention 18.7RTL, CDC, Constraint, or Testbench?

Module 19

SPI in FPGA and SoC Integration

19.1FPGA to ADC — Streaming Under a Sample Deadline 19.2FPGA to Sensor — Register Access and Event-Driven Reads 19.3SoC to SPI Peripheral Through a Register Bus 19.4A Multi-Slave Controller and Its Failure Modes

Module 20

Capstone — Design and Verify a Configurable SPI Controller

20.1Capstone Requirements and Specification 20.2Microarchitecture and Design Decisions 20.3RTL Implementation and Mode Handling 20.4Timing, Constraints, and CDC Considerations 20.5Assertions, Reference Model, and Scoreboard 20.6Constrained Random and Coverage Closure 20.7Bug Injection, Waveform Debug, and Design Review