Mode 2 (CPOL=1, CPHA=0)

Chapter 3.4 built the CPHA = 0 first-bit launch and called it the one piece of hardware the mode bits genuinely require. Chapter 3.5 flipped the phase bit and watched the requirement disappear.

Mode 2 flips the other bit, and the result is the sharpest test of the claim Chapter 3.2 made.

If polarity and phase are truly independent, what should change when only the polarity changes — and what should not?

The prediction is precise: every physical direction should reverse, and every logical behaviour should stay identical. If that holds, the bits do not interact. If anything logical changed, Chapter 3.3's whole derivation would be unsound and the four modes really would be four special cases. This chapter checks the prediction and then works through the consequences that are specific to resting a clock high — which turn out to be board-level rather than protocol-level.

1. Mode 2, Derived

The three steps, once more.

Step 1 — where does the clock rest? CPOL = 1, so SCLK idles high. This is the only input that differs from Mode 0.

Step 2 — which direction is the leading edge? Away from rest, so with the clock resting high, leading is falling and trailing is rising. Both reversed from Mode 0.

Step 3 — which logical edge samples? CPHA = 0, so the leading edge samples and the trailing edge launches. Identical to Mode 0.

Composing: Mode 2 samples on falling edges and launches on rising edges, with the clock idling high.

Compare that against Mode 0 — samples on rising, launches on falling, idles low — and the pattern is exactly the prediction. Every physical direction inverted. The logical description, stated in Chapter 2.2's vocabulary, is word-for-word the same: leading samples, trailing launches.

2. The Transfer

Lay this beside Chapter 3.4's figure and the correspondence is exact. The mosi row is identical — same values, same columns, same transitions. The cs_n row is identical. Only the sclk row is inverted.

That is the independence, drawn. The data timing is a function of the bit-time structure and the phase bit; the clock's shape is a function of the polarity bit; and changing one left the other untouched.

3. What Carries Over Unchanged

Because CPHA = 0 is shared with Mode 0, everything Chapter 3.4 established applies to Mode 2 without modification. It is worth listing explicitly, because the temptation is to treat each mode as needing its own analysis.

The first-bit launch. Mode 2's first sampling edge is the transfer's first edge, so a bit must be present before it. CS assertion launches it, exactly as in Mode 0. The arithmetic argument from Chapter 3.5 §3 applies verbatim: leading edges are spent sampling, the final trailing launch is discarded, and one launch must come from outside the clock.

The CS lead interval's data requirement. It must cover the transmitter's CS-to-output-valid delay, not merely the device's internal preparation.

The slave's asynchronous path problem. An FPGA slave in Mode 2 faces the identical choice Chapter 3.4 §6 described — synchronise CS and lose latency, or drive the output combinationally from an asynchronous pin.

The failure signature. A missing first-bit path produces one wrong bit in the most significant position, reproducibly, at every clock rate.

The RTL. Chapter 3.4's spi_tx_path implements Mode 2 with no change whatsoever, because it takes cpha and never sees cpol at all — polarity is handled entirely upstream, in the divider (Chapter 3.1) and the mode decoder (Chapter 3.3).

4. What Genuinely Differs

If polarity changed nothing at all, it would not be worth a configuration bit. Three things do differ, and none of them is about the transfer.

The line's electrical state when idle. Resting high rather than low has board-level consequences that Chapter 3.1 §3 introduced: it may or may not draw current through a pull resistor, it interacts differently with a level shifter or isolator, and it presents a different state during reset and power sequencing. On a design where SPI idles for the great majority of the time, this can be a real selection criterion.

Bus sharing becomes constrained. All devices on a shared SCLK net see the idle level, and a part that requires the opposite one cannot coexist without the master reconfiguring between transactions — the scenario Chapter 3.1 §11 worked through. Mode 2 is one half of that incompatibility whenever the other device wants Mode 0 or 1.

The physical directions an engineer must look for. When debugging, "data changes on rising" identifies Mode 2's launch and Mode 0's sample. An engineer carrying the physical description rather than the logical one will read the same capture two different ways depending on which mode they assumed — which is precisely why Chapter 2.2 insisted on establishing the idle level first.

5. Mode 2's Partner

Chapter 3.3 §4 noted that modes 0 and 3 agree on both physical directions — launch on falling, sample on rising — differing only in idle level. The complementary statement is true here:

Modes 1 and 2 also agree on physical directions: both launch on rising and sample on falling. Mode 1 gets there with CPOL = 0, CPHA = 1; Mode 2 with CPOL = 1, CPHA = 0. The two bits differ in both positions, and the two inversions cancel.

So the four modes fall into two physical pairs:

That table is worth more than the mode numbers, because it is what a capture actually shows you. A scope tells you which direction launches and which samples; it does not tell you a mode number. Combined with the idle level — the one additional observation Chapter 3.3 §8 requires — it identifies the mode uniquely.

It also explains a practical asymmetry. A device that is genuinely indifferent to the idle level works in either member of its pair. That indifference is common for CPHA = 1 parts and much rarer for CPHA = 0 parts, for a reason worth stating: under CPHA = 0 the device must launch its first bit on CS assertion and then hold it across the clock's departure from idle, so its behaviour is entangled with where the clock was resting. Chapter 3.7 develops the 0-and-3 case, which is the commercially important one.

6. Why This Chapter Has No New RTL

Deliberate, and the reason is the chapter's own thesis.

Chapter 3.4's transmit path already implements Mode 2, unchanged, because polarity never reaches it. The divider (Chapter 3.1) parks at cpol and emits physical strobes; the decoder (Chapter 3.3) maps those onto logical roles using cpol; and the transmit path consumes only the logical launch_stb and the cpha bit. Polarity is fully absorbed before the datapath sees anything.

Writing a "Mode 2 module" would therefore be writing a module that differs from the Mode 0 one in no respect at all — which would actively teach the wrong thing. The architecture's whole merit is that polarity is handled in one place and never again.

The correct representation here is the figure comparison of §2 and the physical-pair table of §5, which are the things you cannot get from code. And the mode decoder's testbench in Chapter 3.3 already verifies Mode 2's role mapping explicitly — the check(2'd2, …) cases confirm that falling samples and rising launches, which is this chapter's derivation executed in simulation.

7. Why an FPGA or ASIC Engineer Cares

The idle level is a pin state, and pin states matter at power-up. An output that must rest high needs to reach that level promptly and stay there through reset. Chapter 3.1 §5 showed why the divider's output register must park at cpol rather than at a constant — Mode 2 is where that matters, because a design defaulting to a low output presents the wrong level to a Mode 2 device for the entire window between power-up and the first configuration write. On an FPGA, the state of a pin before configuration completes is a separate question again, governed by the device's unprogrammed-pin behaviour and any external pull.

A high idle level may need a pull to match. If the board relies on a pull resistor to define SCLK while the master's output is high-impedance — during FPGA configuration, during reset, or on a hot-swappable module — the pull's direction must agree with CPOL. A pull-down on a Mode 2 bus presents the wrong idle level exactly when the master cannot drive, which is a board error that no amount of firmware fixes.

Nothing about timing changes. The round-trip budget, the setup and hold windows, the I/O register arguments and the output-delay constraints are all identical to Mode 0's. Inverting a clock does not move its edges in time; it only changes which direction they point.

8. Failure Signature — A Mode 2 Device on a Bus Configured for Mode 0

Symptom. A device documented for Mode 2 is added to an existing bus that a working Mode 0 device shares. The Mode 2 device returns data that is consistently wrong — often a recognisable but shifted version of the expected value — while the Mode 0 device continues to work perfectly. Reproducible at every clock rate.

Plausible mechanisms. A single configured polarity serving two devices that need different ones is the leading candidate, and it is the specific form of the general problem Chapter 3.1 §11 analysed. Competing explanations are a command-format error specific to the new device, and a device requiring an initialisation sequence the driver omits.

The discriminating observations. First, reproducibility at every rate eliminates margin and round-trip mechanisms — this is configuration, not timing.

Second, compare the two datasheets' mode requirements. Mode 0 and Mode 2 differ only in polarity, so if one part wants each, the incompatibility is established on paper without touching the board.

Third — and this is the useful one — read the idle level on a capture and derive the mode actually present using Chapter 3.3 §8. That tells you what the bus is doing rather than what the driver intends, which matters when a bootloader or another driver has configured the controller first.

Why the corruption is "recognisable but shifted." Because a polarity mismatch displaces the sampling instant by half a bit time relative to the device's expectation — the mechanism Chapter 3.1 §11 described. The device still receives a well-formed clock with the right number of edges; it simply reads each bit at the wrong moment, so the received word is a shifted version of the transmitted one rather than noise. Chapter 3.8 works through the full signature catalogue.

The fix and its cost. Reconfigure polarity between transactions to the two devices, which must happen while no CS is asserted because the parked level moving is an edge every device on the shared net observes. Before adding that machinery, check whether either device is genuinely indifferent to the idle level — §5 explains why that is less likely for CPHA = 0 parts like these two, but the datasheets are the authority.

9. Common Misconceptions

10. Reason It Through

Work this before reading the answers.

A logic-analyser capture from a failing link shows SCLK idling high, data on MOSI changing on rising edges, and the peripheral's datasheet stating that it captures data on the first edge of each clock period. The controller is configured for Mode 1. Determine whether the configuration is correct, and if not, what it should be.

Derive what the device needs. The capture shows the clock idling high, so CPOL = 1 and the leading edge is falling. The datasheet says capture on the first edge of each period — the leading edge — so CPHA = 0. Therefore the device requires mode = (1 << 1) | 0 = Mode 2.

Is the controller's configuration correct? No. It is set to Mode 1, which is CPOL = 0, CPHA = 1. Both bits are wrong, which is the most severe of the mismatch cases and the subject of Chapter 3.8.

But hold on — the capture shows the clock idling high. If the controller is configured for CPOL = 0, why is the clock resting high? This is the most informative question in the exercise, and it has two possible answers. Either the capture was taken with the controller in a different state than the driver believes — a bootloader or an earlier driver configured it and the current code never re-wrote the register — or the idle level is being set by something other than the master, such as a pull resistor while the output is high-impedance. Both are real; both are found by reading the controller's mode register and checking whether the master is actually driving SCLK while idle.

What about MOSI changing on rising edges — is that consistent? With the controller in Mode 1 (CPOL = 0, CPHA = 1), the leading edge is rising and it launches, so MOSI changing on rising is exactly what Mode 1 produces. That observation therefore agrees with the controller's configuration, not with the clock's observed idle level — which is the contradiction that points at the answer above. Two observations disagreeing about what the master is doing means the master is not in one consistent state, and resolving that comes before any mode change.

What is the correct action? First reconcile the contradiction: establish whether the controller is actually in Mode 1 and something else is holding the line high, or whether it is in a different mode than assumed. Then configure for Mode 2, which is what the device requires. Changing the mode register without resolving the contradiction risks fixing the symptom while leaving a second configuration path that will overwrite it again.

The transferable lesson. Cross-checking two independent observations — the idle level and the launch direction — is what exposed the inconsistency. A single observation would have produced a confident, wrong answer either way, and Chapter 3.3 §11 made the same point from the other direction.

11. Understanding Check

12. Summary

Mode 2 is CPOL = 1, CPHA = 0: the clock idles high, the leading edge is falling, and the leading edge samples. So it samples on falling and launches on rising.

Set against Mode 0 it is the cleanest available demonstration that the two configuration bits are independent. Changing only polarity reversed every physical direction and changed no logical behaviour: the data waveform relative to the bit time is bit-for-bit identical, the first bit is still launched by CS, the CS lead interval still carries a data requirement, and Chapter 3.4's transmit path implements Mode 2 with no modification because polarity never reaches it.

That is the practical form of the independence argument: each concern belongs to one bit. Phase owns the first-bit launch, the lead interval's data requirement and the slave's asynchronous path problem. Polarity owns the idle electrical state, the bus-sharing constraint and the power-up pin level. Recognising which bit owns a question is what lets a design support four modes with two multiplexers.

The four modes form two physical pairs: modes 0 and 3 launch on falling and sample on rising; modes 1 and 2 launch on rising and sample on falling. Each pair differs only in idle level. That table is more useful than the numbering, because a capture reveals physical directions while the idle level then identifies the member.

13. What Comes Next

Chapter 3.7 — Mode 3 completes the set with CPOL = 1, CPHA = 1, and takes up the question §5 raised: why modes 0 and 3 are the pair that matters commercially, what a datasheet means when it lists both, and when relying on that is safe.

Browse the path on the SPI curriculum index, or revisit Mode 0 for the logic Mode 2 shares, or CPOL for the bit it flips.