Slave Output Valid Timing

Every requirement so far in this module has been an obligation the master owes: generate a legal clock (Chapter 2.1), separate launch from sample (Chapter 2.3), respect the receiver's aperture (Chapter 2.4), frame the burst with adequate CS gaps (Chapter 2.5).

This chapter turns the relationship around.

How long after the relevant edge may the peripheral take before MISO is trustworthy?

The answer is a number in the device's datasheet, and it is the term that most often dominates the return-path budget. It is also the term engineers most frequently use incorrectly — not because they misread the value, but because they ignore the condition printed beside it.

1. The Term We Have Been Deferring

Chapter 1.6 listed four delays that must fit inside the half period, and named the second one "the slave's clock-to-output time" without examining it. Chapter 2.4's worked budget assumed "the data becomes valid 14 ns after the launch edge" and left the 14 ns unexplained. This is where that number comes from.

Call it t_v — output valid time, also written t_CO, t_DO, t_ACC, or "clock to output" depending on the vendor. It is the maximum interval from the relevant clock edge at the device's pin to the moment MISO is guaranteed to carry the correct new value at that same pin.

Two words in that sentence carry weight.

Maximum. It is a guarantee that the device will not be slower than this. It is not a typical value and not something to average. A budget built from typical values is a budget that fails on some fraction of parts, as Chapter 2.4 §5 argued.

Guaranteed. Before t_v elapses, MISO may be anything: the old bit, the new bit, a level somewhere between them, or — on some devices — a brief excursion as internal logic settles. It is not "probably the new value a bit early." It is undefined, and reading it early is the failure mode this chapter exists to prevent.

2. What t_v Actually Contains

It is worth decomposing, because the decomposition explains why the number behaves the way it does.

Internal propagation. The clock edge arrives at the device's pin, travels through its input buffer, reaches the internal flip-flop that holds the bit being presented, and the resulting value propagates to the output stage. This is silicon delay and it scales with process, voltage and temperature in the usual directions.

Output driver transition. The output stage must then move the external net from one level to the other, and Chapter 1.6 established what that involves: charging or discharging the capacitance of the trace, the receiver's input pin, and everything else attached to the net. This part of t_v is not a property of the device alone — it depends on what the device is driving into.

That second component is the source of the most common error in SPI timing analysis, and it deserves its own section.

3. The Load Condition

Open any SPI device's timing table and look for a note near the AC characteristics. It will say something of the form "C_L = 30 pF" or "output load 50 pF" or "measured with the test circuit of Figure N."

That condition is part of the specification. The published t_v is the delay into that load. Present a larger capacitance and the output driver takes longer to swing the net, so the real t_v on your board is larger than the published number.

Where does extra capacitance come from? Chapter 1.5 already answered: every device attached to the shared MISO net contributes its input capacitance, whether or not it is selected. So do the trace itself, vias, connectors, test points, and a scope probe if one is attached. A two-peripheral bus with a modest trace can easily exceed a 30 pF test condition.

Three practical consequences.

Adding an unselected peripheral can slow down the selected one. Its input capacitance joins the net permanently. This is the mechanism behind Chapter 1.5's observation that a device that is never accessed can lower the rate the bus sustains — and t_v is the term through which it acts.

Vendors sometimes publish a derating figure. Some datasheets give a nanoseconds-per-picofarad slope, or a second t_v at a larger load. When they do, use it. When they do not, the honest position is that you do not know the real value and must either measure it or leave conspicuous margin.

The number can only get worse, never better. A lighter load than the test condition does not entitle you to assume a smaller t_v; the specification is a maximum under stated conditions, not a formula. Treat the published value as a floor for your own estimate.

4. Where t_v Sits in the Bit Time

Read the shaded regions as the budget being consumed. The launch edge starts the clock running on t_v; MISO is undefined, not merely stale, for that whole interval. Only what remains of the half period is available for the signal to cross the board and satisfy the master's setup requirement — the accounting Chapter 2.7 completes.

Notice how little slack there is in the figure. That is deliberate and realistic: on a fast link t_v is typically the largest single term in the return path, often larger than the board propagation and the master's setup combined. When a budget fails, this is usually where the time went.

5. Which Edge Does It Start From?

Two cases, and confusing them costs a half period.

During the transfer, t_v runs from the launch edge. Chapter 2.3 established that one edge of each bit time launches and the other samples. The peripheral presents its next bit on the launch edge, so that is where its output delay starts, and the master's sampling edge arrives a half period later. This is the case Figure 1 draws.

For the first bit, t_v may run from CS. Under the edge-role configuration in which the receiver samples on the leading edge, the first bit must already be on MISO when the first clock edge arrives — there is no earlier edge to launch it. Devices handle this by driving the first bit from the falling edge of CS, and they specify a separate parameter for it: a CS-to-output-valid or CS-to-data-valid time.

That first-bit parameter interacts directly with Chapter 2.5's CS lead requirement, and the interaction is worth stating explicitly: the CS lead interval must be long enough for the device's CS-to-output-valid time as well as for its internal preparation. A master that satisfies the lead requirement but not this one begins clocking before the first bit is trustworthy, and captures garbage in bit position one while every subsequent bit is fine — a first-bit-only corruption distinct from the first-byte corruption of Chapter 2.5.

6. Modelling It in a Testbench

There is no RTL in this chapter, for a reason §9 develops. But there is verification work, and it is directly useful.

A master cannot be verified against an idealised peripheral that responds instantly, because the entire failure mode of this chapter is a peripheral that does not. A slave behavioural model should present MISO after a configurable delay, so that a test can sweep the delay and find the frequency at which the master stops working.

   // Verification code, not RTL. The point is the `#(cfg.t_v)`: a slave that
   // responds instantly cannot exercise the master's capture margin, so a BFM
   // that models zero output delay hides exactly the bug this chapter is about.
   class spi_slave_cfg extends uvm_object;
       `uvm_object_utils(spi_slave_cfg)
       time t_v;            // output valid delay, from the DEVICE datasheet
       time t_v_cs;         // CS-to-output-valid, for the first bit
       function new(string name = "spi_slave_cfg"); super.new(name); endfunction
   endclass

   task automatic drive_miso(spi_slave_cfg cfg, byte unsigned tx);
       int unsigned i = 0;

       @(negedge vif.cs_n);
       vif.miso <= 1'bx;                     // undefined until t_v_cs elapses
       #(cfg.t_v_cs) vif.miso <= tx[7];      // first bit, launched by CS

       forever begin
           @(posedge vif.cs_n or posedge vif.sclk);
           if (vif.cs_n) begin
               vif.miso <= 1'bz;             // release on deselect (Chapter 1.2)
               break;
           end
           i++;
           if (i > 7) continue;
           // Model the real behaviour: UNDEFINED first, then the new value.
           vif.miso <= 1'bx;
           #(cfg.t_v) vif.miso <= tx[7 - i];
       end
   endtask

Three points matter more than the code.

Driving x during the delay is the whole trick. A BFM that simply schedules the new value after a delay leaves the old value on the line in the meantime, so a master that samples early reads the previous bit — which is wrong, but deterministically wrong, and may accidentally match expectations. Driving x makes an early sample propagate an unknown into the scoreboard, which fails loudly. This is the difference between a model that finds the bug and one that hides it.

The delays belong in a configuration object. Same argument as Chapter 2.2's resting level and Chapter 2.5's CS intervals: they are properties of the attached device, populated from its datasheet, not constants baked into the agent.

A delay sweep is the useful test. Rather than one value, sweep t_v upward until the master fails, and compare the breaking point against the budget you calculated. Agreement validates your analysis; disagreement means the model or the analysis is wrong, and either is worth knowing. Module 16 builds this into a proper environment.

7. Measuring It on a Bench

When a datasheet's condition does not match your board — or when there is no published derating — measurement is the fallback, and it is straightforward with the right instrument.

Put an oscilloscope on SCLK and MISO at the peripheral's pins, trigger on the launch edge, and measure to the point where MISO has settled to a valid level. Chapter 2.4 §8 explains why this must be a scope rather than a logic analyser: you are measuring an analogue settling time of a few nanoseconds, and a logic analyser's own threshold behaviour is comparable to the quantity of interest.

Three cautions that make the difference between a number and a misleading number.

Probe at the pins, not at a convenient via. t_v is specified at the device's output pin, and adding trace between the pin and the probe adds propagation you will wrongly attribute to the device.

The probe changes what you measure. Its capacitance joins the net, increasing the load and therefore lengthening the very delay you are measuring. A low-capacitance probe matters here, and the measured value is an upper bound on the unprobed one.

Measure at the worst corner you can reach. t_v grows with temperature and falls with supply voltage. A room-temperature, nominal-supply measurement is the best case, and the number you need for a budget is the worst.

8. Why an FPGA Engineer Cares — Both Directions

The asymmetry from Chapter 1.2 reappears, and it changes who owns this parameter.

As master, t_v is a number you read from somebody else's datasheet and budget against. You do not control it; you control the frequency and the board that must accommodate it.

As slave, t_v is yours. Your design's delay from the SCLK edge arriving at your pin to valid data at your MISO pin is the peripheral output-valid time that the other end's master must budget against — and if it is too large, the master cannot run at the rate its own datasheet reading suggested. Three implementation facts follow.

The path is longer than it looks. It runs from the SCLK input pin, through the input buffer, into the fabric, through whatever clocking arrangement the slave uses, to the MISO output register, and out through the output buffer. Each stage adds delay.

An I/O output register is the single most effective improvement. Driving MISO from a register in the I/O block rather than from fabric logic removes routing delay from the critical part of the path and — more importantly — makes it constant across builds. The same point Chapter 2.1 made for SCLK, now with a directly quantified consequence.

It must be constrained, or it is not a number at all. The delay from the internal register to the pin is bounded only if an output delay constraint declares what the external world requires. An unconstrained MISO path has whatever delay the router happened to produce, varying between builds. Module 15 covers writing the constraint; Module 14 builds the slave whose path this is.

For an ASIC the same structure applies with pad delays and I/O timing constraints at the boundary, and the published t_v in your device's datasheet is a number your timing signoff must guarantee.

9. Why There Is No RTL in This Chapter

Deliberate. t_v is a characteristic of a device you did not design, measured at its pins — it is not implemented by any HDL you write. The one case where you do own it is the FPGA-as-slave case in §8, and there the answer is not new RTL but where the output register sits and what constrains it, which is architecture and constraints rather than code. Chapter 1.3's shift core already showed the register that drives the output; nothing in this chapter changes it.

Writing a synthesizable module here to satisfy a quota would teach the wrong lesson — that output delay is something you code rather than something you budget, measure and constrain. The correct representations for this chapter are the waveform, the load condition, the measurement procedure and the behavioural model, which §3 to §7 provide.

10. Failure Signature — The Controller Captures the Previous Bit

Symptom. A read returns data that is the correct value shifted by one bit position. It is not random. It appears above a certain clock rate and disappears below it, and the transmitted direction (MOSI) is unaffected.

Candidate mechanisms. The master is sampling MISO before the peripheral's output has settled, so it captures the previous bit — t_v plus board propagation plus setup exceeds the half period. The competing explanations produce the same one-position offset and must be separated: an inverted edge-role configuration (Chapter 2.3), a wrong resting level (Chapter 2.2), or a first-bit launch problem.

The discriminating observation — and it is decisive. Is the symptom frequency-dependent? A t_v shortfall is: the half period shrinks as the clock rises while t_v does not, so there is a rate below which it works and above which it does not. Configuration errors are frequency-independent and produce the identical offset at every rate, as Chapter 2.2 established. One frequency sweep partitions the entire hypothesis space, and it requires no instruments.

Then confirm directly. Scope SCLK and MISO at the master's pin, trigger on the master's sampling edge, and look at where MISO settles relative to it. If the line is still moving at the sampling instant, the budget is exhausted and this chapter's term is the reason.

Why it looks like a "one bit shift" rather than corruption. Because capturing before t_v elapses reliably yields the old bit on most real devices — the output has not yet begun to change, or has not changed enough to cross the threshold. So the whole received stream is offset by one position rather than randomly wrong, which is exactly why it is so easily mistaken for a mode misconfiguration. The frequency dependence is the only thing that separates them cheaply.

11. Common Misconceptions

12. Reason It Through

Work this before reading the answers.

A design reads an ADC at 8 MHz with no trouble. A second, unrelated peripheral is added to the same SCLK, MOSI and MISO nets, with its own chip select. The ADC reads now fail intermittently — but only above about 6 MHz. Nothing about the ADC, its wiring, or the firmware changed, and the new peripheral is never selected.

Why is "the new peripheral is never selected" not exculpatory? Because selection is a logical mechanism and loading is a physical one. The new device's input pin is connected to the MISO net permanently, so its input capacitance joins the net the moment it is fitted. Chapter 1.5 made this point structurally; this chapter supplies the term through which it acts.

Which term in the budget changed? t_v for the ADC. Its output driver now has more capacitance to charge, so the interval from the launch edge to a settled MISO level grew. Nothing about the ADC changed — its silicon delay is the same — but the driver-transition component of t_v is a function of the load, and the load changed.

Why does the failure have a frequency threshold? Because the half period is what t_v competes against. At 6 MHz the half period is about 83 ns and the enlarged t_v still fits with margin; at 8 MHz it is 62.5 ns and it does not. The threshold is simply where the grown t_v plus propagation plus setup equals the shrinking budget.

Why intermittent rather than a clean cut-off? Because the terms vary. t_v moves with temperature and supply; the sampled level near the threshold depends on the previous bit through the settling of the edge. Just past the limit some captures land on the right side of the threshold and some do not, which produces exactly the data-dependent intermittency Chapter 2.4 §2 described.

What is the decisive measurement? Scope MISO at the master's pin, triggered on the master's sampling edge, both with the new peripheral fitted and with it removed or depopulated. A visible increase in settling time between the two, with everything else unchanged, confirms the mechanism directly and quantifies it.

What are the options, and which is the trap? Reduce the load — shorter routing, fewer stubs, or moving the new device to a separate MISO net if the controller has one. Widen the window with a delayed sampling point if the controller offers it (Chapter 2.7). Or lower the clock and accept the throughput, documenting why. The trap is concluding the ADC is faulty and replacing it: the part is behaving exactly as specified, under a load the specification never promised anything about.

13. Understanding Check

14. Summary

The peripheral's output valid time — t_v, variously t_CO, t_DO or clock-to-output — is the maximum interval from the relevant edge at the device's pin to guaranteed-correct data at the same pin. Before it elapses MISO is undefined, not stale, and sampling there is what produces the classic one-position offset in received data.

It decomposes into internal propagation plus the output driver's transition into the load, and the second part is why the published number is conditional. Datasheets state a test load; your board almost certainly presents a heavier one, so your real t_v exceeds the published figure. Every device attached to the shared MISO net contributes capacitance whether or not it is selected — which is the mechanism by which an unused peripheral can slow an existing link.

During the transfer t_v runs from the launch edge, leaving only the remainder of the half period for board propagation and the master's setup requirement. For the first bit under one edge-role configuration it runs instead from CS falling, which means Chapter 2.5's lead interval must accommodate it too.

On a fast link this is usually the largest single term in the return path — and, because it is conditional on load, the one most likely to have been under-estimated. When a budget fails, look here first.

There is no RTL here because t_v belongs to a device you did not design; the exception is the FPGA-as-slave case, where the answer is an I/O output register and an output delay constraint rather than new code. In verification the essential move is a slave model that drives x for the delay rather than holding the old value, so that an early sample fails loudly instead of silently returning a plausible wrong bit.

15. What Comes Next

Every term is now on the table: Chapter 2.1 set the period, Chapter 2.3 reduced the usable budget to a half period, Chapter 2.4 named the receiver's requirement, and this chapter supplied the peripheral's contribution. Chapter 2.7 — Master Input Capture and Round-Trip Delay assembles them into the complete loop — clock out across the board, device response, data back, master capture — and derives why the practical maximum SCLK is a property of a whole system rather than of any device in it. It closes the module.

Browse the path on the SPI curriculum index, or revisit Electrical and Board-Level Limits for the load and edge-rate physics this chapter's second component comes from.