Mode 1 (CPOL=0, CPHA=1)

Chapter 3.4 spent most of its length on one problem: under CPHA = 0 the first clock edge samples, so a bit must be on the line before any edge exists, and the transmitter needs a second launch path driven by chip select.

Mode 1 keeps the same clock and flips the phase bit. The entire problem disappears.

What does CPHA = 1 actually buy, and what does the resulting symmetry reveal about a transfer's structure?

This chapter is short on new mechanism by design — everything it needs was built in Chapter 3.3 and Chapter 3.4. Its work is comparison, and the comparison exposes a structural fact about SPI transfers that is easy to miss when you only ever look at one mode.

1. Mode 1, Derived

The three steps from Chapter 3.3, again.

Step 1 — where does the clock rest? CPOL = 0, so SCLK idles low. Identical to Mode 0.

Step 2 — which direction is the leading edge? Away from rest, so leading is rising and trailing is falling. Also identical to Mode 0.

Step 3 — which logical edge samples? CPHA = 1, so the trailing edge samples and the leading edge launches. This is the only difference.

Composing: Mode 1 launches on rising edges and samples on falling edges, with the clock idling low.

Note what that means physically against Mode 0: the two modes have the same clock waveform and exchange the roles of its two edges. On a scope, a Mode 0 and a Mode 1 transfer of the same data look identical on SCLK and differ only in where the data transitions sit relative to it.

2. The Transfer

Set this beside Chapter 3.4's figure and one difference accounts for everything.

At column 1, the line is undefined. In Mode 0 it already carried b2, launched by CS. Here nothing has been launched, because nothing needed to be — the first sampling edge is column 3, not column 2, and the launch at column 2 happens first.

Every bit follows the same rule. Launch on the rising edge that opens the bit time, sample on the falling edge that closes it. Bit one is not special. That uniformity is the entire content of CPHA = 1.

3. The Edge Accounting

Here is the structural fact that only becomes visible when you compare the two phases: their edge budgets do not balance the same way.

Take an N-bit transfer. It contains 2N clock edges — N leading and N trailing (Chapter 3.1 §4 established that a transfer always has an even number).

Under CPHA = 1: each leading edge launches a bit and each trailing edge samples one. N launches, N samples, 2N edges, every edge doing useful work. The accounting is exact.

Under CPHA = 0: each leading edge samples and each trailing edge launches. So the N leading edges account for the N samples — but the N bits had to be launched by something, and only N - 1 of them came from trailing edges. The missing one is the CS launch. And at the other end, the final trailing edge launches a bit that no subsequent edge ever samples, because the transfer is over.

So CPHA = 0 has an extra launch at the start (from CS) and a wasted launch at the end (into nothing), while CPHA = 1 has neither.

That asymmetry is directly assertable, and the assertion is a good structural check on a mode-configurable design:

   // Count strobes across one CS assertion. Under CPHA=1 the counts must match
   // exactly; under CPHA=0 the launches lag by one, because CS supplied the
   // first and the final trailing launch is discarded.
   int n_launch, n_sample;

   always_ff @(posedge clk or negedge rst_n) begin
       if (!rst_n) begin
           n_launch <= 0;
           n_sample <= 0;
       end else if (cs_n) begin             // between transfers: reset the tally
           n_launch <= 0;
           n_sample <= 0;
       end else begin
           if (launch_stb) n_launch <= n_launch + 1;
           if (sample_stb) n_sample <= n_sample + 1;
       end
   end

   // Checked on the deasserting edge of CS, when the transfer is complete.
   property p_edge_balance;
       @(posedge clk) disable iff (!rst_n)
           $rose(cs_n) |-> (cpha ? (n_launch == n_sample)
                                 : (n_launch == n_sample));
   endproperty

That last property deserves a caution, because it is written to look right and is worth examining. Counting strobes gives equal totals in both phases — the decoder issues one launch and one sample per bit time regardless. What differs is not the strobe count but which of them carry useful data: under CPHA = 0 the first launch comes from CS (not a strobe at all) and the final launch strobe is discarded. So an assertion over strobe counts cannot see the asymmetry; only an assertion that also observes the CS launch event can. State the invariant over the thing that actually differs, or the check passes vacuously — a good general lesson about writing properties against the right signal.

4. What the Symmetry Buys

Four concrete consequences, in descending order of how much they matter.

No second launch path. The transmitter presents the next bit on every launch strobe and nothing else. Chapter 3.4's live flag is still present in a mode-configurable design — it is what makes one datapath serve both phases — but under CPHA = 1 it is set by the first launch strobe, which is an ordinary path rather than a special one.

No data requirement on the CS lead interval. Chapter 3.4 §3 added the transmitter's CS-to-output-valid delay to the lead interval's obligations. Under CPHA = 1 the first bit is launched by an edge and has a full half period to settle, exactly like every other bit. The lead interval reverts to covering only the device's internal preparation, as Chapter 2.5 originally described.

No asynchronous pin-to-output path in a slave. This is the big one for FPGA work. Chapter 3.4 §6 described the unattractive choice a CPHA = 0 slave faces — synchronise CS and lose latency from the master's lead interval, or drive MISO combinationally from an asynchronous pin. Under CPHA = 1 the first bit is launched by a clock edge like every other, so no such path exists and the question does not arise.

One fewer failure mode. The single-wrong-first-bit signature of Chapter 3.4 §7 cannot occur, because there is no first-bit special case to omit or to run out of time.

5. The Last Bit, and the CS Lag Interval

The symmetry has one consequence at the other end of the transfer that is worth drawing out, because it runs the opposite way.

Under CPHA = 1, the final bit is sampled on the last trailing edge — the very last edge of the transfer. Everything after that edge is CS lag (Chapter 2.5) and then release.

Under CPHA = 0, the final bit is sampled on the last leading edge, which is the second-to-last edge. There is then a whole half period — the final trailing edge and its aftermath — before CS releases.

So CPHA = 0 gives the receiver slightly more breathing room at the end of a transfer, while CPHA = 1 concentrates the last capture right against the CS lag interval. In practice this rarely limits anything, because the lag requirement is usually generous compared with a half period. It matters in one situation: a device whose CS lag requirement is specified in absolute time and a link running fast enough that a half period is comparable to it. Then the CPHA = 1 case has less margin between its final capture and CS deassertion, and it is worth checking rather than assuming.

The general point is that the phase bit does not simply move a convenience from one end to the other — CPHA = 0 front-loads the difficulty and CPHA = 1 back-loads it, and the front-loaded one is much the more troublesome because it involves a signal other than the clock.

6. Where Mode 1 Is Actually Used

Modes 0 and 3 dominate (Chapter 3.3 §4), so it is fair to ask where Mode 1 appears.

Devices that specify CPHA = 1 deliberately. Some converters and sensors document Mode 1 because their internal capture is naturally aligned that way, and a few explicitly cite the absence of the first-bit requirement as an implementation simplification for the host.

Designs where the slave is the constrained end. When an FPGA or microcontroller is the peripheral rather than the controller, CPHA = 1 removes the asynchronous CS-to-output path entirely. If the host's mode is configurable — Chapter 3.2 §10 worked through exactly this decision — choosing Mode 1 or Mode 3 makes the slave meaningfully easier to build and to close timing on.

As the partner of Mode 2. Just as modes 0 and 3 pair by physical direction, modes 1 and 2 form the complementary pair: both launch on one physical direction and sample on the other, mirrored. Chapter 3.6 develops that relationship.

It is also worth saying plainly that Mode 1 is not rare enough to ignore. A controller that supports only modes 0 and 3 — a real and common limitation — will eventually meet a part it cannot drive, and the workaround at that point is usually a board change rather than a software one.

7. Why This Chapter Has No New RTL

Deliberate, and the justification is concrete rather than a shrug.

Chapter 3.4's spi_tx_path already implements Mode 1, and its testbench already proves it: the run_word(1'b1) case drives the same word with cpha = 1, verifies that CS does not launch a bit, verifies that the first launch strobe does, and checks the full MSB-first sequence. That test passed alongside the CPHA = 0 case.

Writing a new module here would reproduce roughly forty lines across three languages to exercise a path already built, already explained and already verified. That is precisely the code inflation this curriculum avoids — and worse, it would obscure the actual lesson, which is that one datapath serves both phases and the difference is which event sets a single flag.

What this chapter adds instead is the edge accounting of §3 and the asymmetry analysis of §5, neither of which is expressible as a module. The correct representation here is the comparison, and §3's assertion discussion shows that even the natural-looking property needs care to state over the right signal.

8. Why a Verification Engineer Cares

Mode 1 is the control case for Mode 0's bug. If a design fails in Mode 0 and passes in Mode 1 with identical stimulus, the fault is in the first-bit path — that single comparison eliminates the entire shared datapath from suspicion. Running both phases against the same reference data is therefore a high-value pair of tests, not two redundant ones.

The coverage cross from Chapter 3.3 §7 earns its place here. Mode crossed with transfer length matters because the CPHA = 0 special case is proportionally most visible in short transfers. Mode 1 needs no such weighting — which is itself the point: a coverage model that treats all four modes as interchangeable bins is missing that two of them have a path the others do not.

Watch for vacuous properties. §3 showed a plausible-looking assertion that cannot detect the asymmetry it was written for, because it counts strobes rather than the events that actually differ. That is a general hazard with structural properties: a check that passes on both the correct and the broken design is worse than no check, because it consumes review attention and confers false confidence. Write the property over the signal that changes.

9. Failure Signature — Mode 0 Fails, Mode 1 Works, Same Device

Symptom. A device documented as supporting both Mode 0 and Mode 1 works correctly when the controller is configured for Mode 1 and returns data with a corrupt first bit in Mode 0. Reproducible in both cases.

Plausible mechanisms. The controller's CPHA = 0 first-bit launch is missing or too slow — the two mechanisms Chapter 3.4 §7 separated. A competing explanation is that the device's first-bit path is at fault rather than the controller's, which matters because it changes who has to fix it.

The discriminating observations. First, the mode comparison itself is already strong evidence: everything except the first-bit path is shared between the two configurations, so a fault present in one and absent in the other is localised to that path before any measurement.

Second, which direction is corrupt? If the data the controller sends is misread by the device, the controller's transmit first-bit path is at fault. If the data the controller receives is wrong in its first bit, the device's transmit path — or the controller's capture of it — is implicated. The two ends have independent first-bit implementations (Chapter 3.4 §3), and this question separates them.

Third, constant or intermittent? Constant means a missing path; intermittent means a lead interval marginal against the output-valid delay.

The temptation to resist. Configuring the link for Mode 1 permanently makes the symptom vanish and is a perfectly reasonable decision if both ends support it and the constraint is documented. It is not a diagnosis, and if the same controller must later drive a Mode 0-only device, the unfixed path resurfaces on a different board with no obvious connection to this one.

10. Common Misconceptions

11. Reason It Through

Work this before reading the answers.

You are reviewing an SPI master IP that supports all four modes. Its transmit path has a single launch input and no connection to chip select anywhere in the datapath. The author states that it has been tested against a Mode 1 device and a Mode 3 device, both successfully, and proposes to sign it off as supporting all four modes.

What is structurally missing? The CPHA = 0 first-bit launch. With no connection from CS into the transmit datapath, the design has no way to place a bit on the line before the first clock edge — so in modes 0 and 2 the first bit cannot be launched at all. The absence is visible in the port list, before reading any logic.

Why did the tests pass? Because both devices tested are CPHA = 1 modes. Mode 1 and Mode 3 launch every bit, including the first, on a clock edge — precisely the path the design does implement. The test evidence is real and entirely irrelevant to the claim being made.

What would the failure look like when it appears? A single wrong bit in the most significant position of every transmitted word, reproducible, unaffected by clock rate — Chapter 3.4 §7's signature. And it would appear only on modes 0 and 2, which is to say on the most common mode in the ecosystem.

What is the correct review outcome? Reject the mode-support claim, not the IP. The design is sound for CPHA = 1 and should be documented as such until the launch path exists. Then require two things for sign-off: the CS launch path itself, and test evidence in a CPHA = 0 mode — because the existing evidence cannot distinguish a design that supports four modes from one that supports two.

What does this say about coverage? That mode coverage measured as four bins would have reported 50% and looked like a gap to fill with more stimulus, when the real gap was structural. And if the tests had been run with the mode register swept — without a device that actually exercises the transmit path in CPHA = 0 — it could have reported 100% while the defect remained. Coverage of a configuration is not coverage of the behaviour that configuration selects, which is why Chapter 3.3 §7 crossed mode with direction and length rather than counting modes alone.

12. Understanding Check

13. Summary

Mode 1 is CPOL = 0, CPHA = 1: the clock idles low and is waveform-identical to Mode 0, but the leading (rising) edge launches and the trailing (falling) edge samples.

That single change removes everything Chapter 3.4 had to build. There is no CS launch path, because the first sampling edge is the transfer's second edge and a launching edge always precedes it. There is no data requirement on the CS lead interval, because the first bit gets a full half period like every other. And in a slave there is no asynchronous pin-to-output path, which is the most valuable of the three for FPGA implementation.

The reason is arithmetic rather than convention. An N-bit transfer has N leading and N trailing edges; under CPHA = 0 the leading edges are spent sampling and the final trailing launch is discarded, leaving N - 1 useful launches for N bits — so one must come from outside the clock. Under CPHA = 1 the accounting balances exactly.

The asymmetry does have a counterpart at the far end: CPHA = 1 concentrates the final capture against the CS lag interval, where CPHA = 0 leaves an extra half period. That rarely binds, and when it does it is because a device specifies lag in absolute time on a fast link.

No new RTL was needed, because Chapter 3.4's transmit path already implements and verifies both phases — the difference being which event sets a single flag. What this chapter adds is the comparison, and a caution worth carrying: a strobe-counting assertion cannot detect the phase asymmetry and passes vacuously on a broken design. State a property over the signal that actually changes.

14. What Comes Next

Chapter 3.6 — Mode 2 inverts the clock and keeps CPHA = 0. It is the cleanest available demonstration that the two bits are genuinely independent: everything Chapter 3.4 established about the first-bit problem applies unchanged, with every physical direction reversed — which is only possible if polarity and phase really do not interact.

Browse the path on the SPI curriculum index, or revisit Mode 0 for the special case this chapter removes, or CPHA for the bit that removes it.