Handshake Comparison

The most common thing said about these two protocols is that AXI's handshake is different from Wishbone's. It is not. Read the two specifications side by side and they describe the same mechanism in almost the same words.

The handshake is the same idea twice. What differs is how many of them run at once — and that forces AXI to state a rule Wishbone never needs.

1. The Same Sentence, Written Twice

Wishbone B3, §Handshaking Protocol:

"All bus cycles use a handshaking protocol between the MASTER and SLAVE interfaces... The MASTER asserts [STB_O] when it is ready to transfer data. [STB_O] remains asserted until the SLAVE asserts one of the cycle terminating signals [ACK_I], [ERR_I] or [RTY_I]. At every rising edge of [CLK_I] the terminating signal is sampled. If it is asserted, then [STB_O] is negated. This gives both MASTER and SLAVE interfaces the possibility to control the rate at which data is transferred."

AMBA AXI, IHI 0022H, A3.2.1 Handshake process:

"All five transaction channels use the same VALID / READY handshake process to transfer address, data, and control information. This two-way flow control mechanism means both the master and slave can control the rate that the information moves between master and slave."

2. Both Sides Hold Their Request Until It Is Taken

Same obligation, same reason. A destination that needs three clocks to answer must still be looking at the same request on the third clock.

3. The Rule AXI Needs And Wishbone Does Not

Here is the first genuine asymmetry, and it exists because of the channels.

IHI 0022H, A3.3.1 — Dependencies between channel handshake signals:

"VALID signal of the AXI interface sending information must not be dependent on the READY signal of the AXI interface receiving that information. An AXI interface that is receiving information can wait until it detects a VALID signal before it asserts its corresponding READY signal."

Read it as what it is: a deadlock-prevention rule. If a source may wait for READY before raising VALID, and the destination waits for VALID before raising READY, nothing ever happens. So the specification forbids one direction of that dependency and permits the other.

Wishbone has no such rule and needs none. With one phase, there is only one handshake, and [STB_O] is asserted because the master has work — not because the slave said anything. The deadlock is not available.

// ── THE DEPENDENCY RULE THIS MASTER MUST NOT BREAK ──────────────────────
// "VALID signal of the AXI interface sending information must not be
// dependent on the READY signal of the AXI interface receiving that
// information."                            (ARM IHI 0022H, A3.3.1)
//
// For a master that means AWVALID must not wait for AWREADY, ARVALID must
// not wait for ARREADY, and WVALID must not wait for AWREADY. The spec
// spells the last one out: a master "must not wait for AWREADY to be
// asserted before driving WVALID".
//
// "When VALID is asserted, it must remain asserted until the handshake
// occurs, at a rising clock edge when VALID and READY are both asserted."
//                                          (ARM IHI 0022H, A3.2.1)
//
// So a raised VALID here is sticky and its payload is held.

4. The Two Handshakes On One Timebase

A single write, on both protocols, into slaves that take three extra clocks to answer.

Both protocols finished the write on the same clock. That is not the point of the figure.

The point is cycle 2. On the Wishbone side STB_O is still asserted and ADR_O still holds 0x020, because RULE 3.35 makes the termination the answer to that request — the address has to still be there for the answer to mean anything. On the AXI side AWVALID has already dropped: the address was taken at cycle 1 and the write address channel is free from cycle 2 onward.

Three clocks of an idle address channel is what AXI bought with its extra complexity. Whether anything can be put in them is Chapter 20.3's question, and the answer is it depends on the slave.

5. The Same Thing, Measured

SIM A runs one workload record on both rigs with zero-wait-state slaves and prints every signal.

  === SIM A - one transfer each, same workload record ===
    workload entry 0 is a READ of word 0x010. Both rigs hold
    the same memory: mem[k] = 0xAAAA_0000 + k. Both slaves
    are set to zero wait states. Nothing differs but the
    protocol.

    clk  WISHBONE                      AXI4-LITE
         CYC STB WE ADR   ACK  DAT     ARV ARR ADDR  RV RR DATA
      2   0   0   0  0x010  0  0xaaaa0010  0   1  0x000  0  1 0x00000000
      3   1   1   0  0x010  1  0xaaaa0010  1   1  0x010  0  1 0x00000000
      4   0   0   1  0x020  0  0xaaaa0020  0   1  0x010  0  1 0x00000000
      5   1   1   1  0x020  1  0xaaaa0020  0   1  0x010  1  1 0xaaaa0010
      6   0   0   0  0x011  0  0xaaaa0011  0   1  0x010  0  1 0xaaaa0010
      7   1   1   0  0x011  1  0xaaaa0011  1   1  0x011  0  1 0xaaaa0010
      8   0   0   1  0x021  0  0xaaaa0021  0   1  0x011  0  1 0xaaaa0010
      9   1   1   1  0x021  1  0xaaaa0021  0   1  0x011  1  1 0xaaaa0011

    transfer 0 result   Wishbone 0xaaaa0010   AXI 0xaaaa0010
    expected                     0xaaaa0010
    (both latched on the clock their own termination
     qualified them, not sampled off the bus afterwards)

    -> B3 RULE 3.35: the termination is "generated in

With no wait states the two protocols are nearly indistinguishable, which is worth seeing before any performance argument begins. The AXI read data arrives one clock later because this module's AXI-Lite slave registers its response while the Wishbone RAM answers combinationally — a slave implementation choice B3 explicitly permits under PERMISSION 3.10, not a protocol difference. Chapter 20.3 §3 returns to that with the numbers.

6. Write Data Before Its Address — A3.3.1's Own Example

The specification does not merely permit the channels to be unrelated; it gives an example, and the example is the one that catches people out.

"The lack of relationship means, for example, that the write data can appear at an interface before the write address for the transaction. This can occur if the write address channel contains more register stages than the write data channel." — IHI 0022H, A3.3.1

Read the second sentence as a warning about integration, not about protocol. Nobody designs a master that deliberately sends write data first. It happens because somebody put a register stage in one path and not the other — a pipeline stage, a clock crossing, an interconnect that buffers addresses — and the ordering the designer assumed silently stopped holding.

A slave that captured its write data only after seeing an address would work on the bench and fail in the system. This module's AXI-Lite slave captures each channel in its own unconditional if, and axi_chan_probe counts how often data actually arrived first:

      // write data ahead of its address is explicitly legal and is the
      // most visible proof that AW and W are not one channel
      if (w_hs && !aw_hs && (nw_q >= naw_q)) wfirst_q <= wfirst_q + 16'd1;

On this module's workload that counter reads zero, because the master raises AWVALID and WVALID on the same clock and the slave accepts both. That is a property of this pairing, not of AXI, and stating it is the difference between a measurement and a claim — a system with one more register stage on the address path would make the same counter non-zero without anything being redesigned.

Wishbone cannot pose the question. [DAT_O()] is qualified by [STB_O] along with [ADR_O]; they are one context and arrive together by construction.

7. Reading The SIM A Trace Clock By Clock

The trace in §5 rewards a slower read. Taking the Wishbone columns first:

Four clocks, two complete transfers. Now the AXI columns over the same window:

The one-clock lag is the registered response, and it is worth being precise about whose choice it is. B3 permits a combinational ACK_O explicitly. AXI does not forbid a combinational RVALID either — but a slave that drives RVALID combinationally from ARVALID is unusual, and one that drove it from RREADY would violate A3.3.1 outright, which Chapter 20.5 §5 measures.

So the honest reading of SIM A is: with zero-wait-state slaves these protocols are separated by one clock of ordinary slave design, and nothing about the protocols themselves shows up at all. Everything interesting needs slower slaves, which is Chapter 20.3.

8. What A Wishbone Master Cannot Express

// wb_master_seq — a Wishbone MASTER that walks the shared workload.
//
// It issues transaction n, waits for its termination, then issues n+1.
// THAT IS NOT A DESIGN CHOICE. It is what the specification's own
// structure permits:
//
//   "The cycle termination signals [ACK_O], [ERR_O], and [RTY_O] must be
//    generated in response to the logical AND of [CYC_I] and [STB_I]."
//                                                   (B3, RULE 3.35)
//
// The termination is generated IN RESPONSE TO the request. There is one
// request context on the wires - [ADR_O], [DAT_O()], [SEL_O()], [WE_O],
// all qualified by [STB_O] per RULE 3.60 - so there is exactly one
// question outstanding, and its answer is the answer to that question.
// Present a second address and you have destroyed the first one.
//
// "The SINGLE READ / WRITE cycles perform one data transfer at a time."
//                                                   (B3, section 3.2.1)
//
// So this master has no MAXOUT parameter. It could not use one. Chapter
// 20.3 counts what that costs and Chapter 20.1 explains why the cost is
// structural rather than an implementation shortcoming.

wb_master_seq has no "maximum outstanding" parameter and could not be given one. That is not a limitation of this implementation. There is one [ADR_O] on the pins and RULE 3.60 qualifies it with [STB_O]; a second address would overwrite the first.

The AXI master in the same testbench has exactly that parameter, and Chapter 20.3 sets it to 1 to show its results landing on top of Wishbone's.

9. Counting The Handshakes Instead Of Describing Them

SIM B runs the full 16-record workload and counts every channel handshake.

  === SIM B - channel independence, counted ===
    the whole 16-transaction workload has now run on both
    rigs. These are the AXI side's channel counters.

      AW handshakes                         7
      W  handshakes                         7
      B  handshakes                         7
      AR handshakes                         9
      R  handshakes                         9

      addresses accepted while an answer was still
      outstanding    writes 0   reads 1
      deepest outstanding   writes 1   reads 1
      write data accepted at or ahead of its address  0

Seven writes and nine reads, and every channel handshake balances against them. Seven AW, seven W, seven B; nine AR, nine R.

And one decoupled acceptance — a single occasion on which an address was taken while an earlier transaction had not been answered. One, on a sixteen-record workload, with fast slaves. That number is small because there was almost nothing to overlap, and Chapter 20.3 shows it reaching 14 the moment the slaves get slower.