Wishbone — Tutorials · VLSI Mentor

174Total chapters

31Modules

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31 / 31Active modules

Buses before signals

Why on-chip buses exist, memory-mapped IO, and open-source SoC interconnect come first — so CYC/STB/ACK and address decoding land on a real mental model.

Interview-ready depth

A leveled interview module plus per-chapter interview weighting — the handshake, decoding, arbitration, RMW, and the Wishbone-vs-AXI questions that trip candidates.

Design → verify → debug

Master/slave/interconnect RTL, a UVM agent, and waveform debugging for missing-ACK, wrong-decode, and arbitration bugs — plus RISC-V/LiteX integration.

Wishbone Complete Curriculum

Your Learning Roadmap

174 chapters · 31 modules — the open on-chip bus — CYC/STB/ACK handshake, decoding, and arbitration.

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Module 1

Why Wishbone Exists

1.1CPU to Peripheral Communication 1.2Memory-Mapped IO 1.3Need for Standardized Interconnects 1.4The Open Hardware Movement 1.5FPGA Design Challenges 1.6OpenCores Origins 1.7Why Wishbone Was Created

Module 2

On-Chip Bus Fundamentals

2.1Masters and Slaves 2.2Address Space 2.3Data Transfer 2.4Control Signals 2.5Bus Transactions 2.6Shared Resources 2.7SoC Communication

Module 3

Wishbone Architecture Overview

3.1Wishbone Architecture Overview 3.2The Wishbone Mental Model 3.3The Master Interface 3.4The Slave Interface 3.5The Interconnect 3.6Data Flow 3.7Transaction Lifecycle

Module 4

Wishbone Signals Deep Dive

4.1CLK_I 4.2RST_I 4.3ADR_O 4.4DAT_O 4.5DAT_I 4.6WE_O 4.7SEL_O 4.8STB_O 4.9CYC_O 4.10ACK_I 4.11ERR_I 4.12RTY_I

Module 5

Basic Wishbone Handshake

5.1The Wishbone Handshake 5.2CYC — Cycle 5.3STB — Strobe 5.4ACK — Acknowledge 5.5Transaction Initiation 5.6Transaction Completion 5.7Timing Relationships 5.8Handshake Rules

Module 6

Read Transactions

6.1Read Cycle Flow 6.2Address Phase 6.3Data Return 6.4ACK Generation 6.5Wait States 6.6Waveform Analysis

Module 7

Write Transactions

7.1Write Cycle Flow 7.2Data Transfer 7.3ACK Timing 7.4Wait States 7.5Waveform Analysis

Module 8

Bus Cycles

8.1Single Read Cycle 8.2Single Write Cycle 8.3Block Transfer Cycle 8.4Read-Modify-Write Cycle 8.5Cycle Types 8.6Performance Considerations

Module 9

Wait States

9.1Why Wait States Exist 9.2Slave Delays 9.3ACK Delay 9.4Transaction Extension 9.5Common Bugs

Module 10

Error Handling

10.1The ERR Signal 10.2Error Responses 10.3Invalid Accesses 10.4Timeout Handling 10.5Debug Strategies

Module 11

Retry Mechanism

11.1The RTY Signal 11.2Retry Concepts 11.3Temporary Resource Unavailability 11.4Transaction Restart 11.5Real Examples

Module 12

Address Decoding

12.1Address Decoding 12.2Address Maps 12.3Decoder Logic 12.4Peripheral Selection 12.5Memory Selection 12.6Default Slave 12.7Sparse Address Spaces

Module 13

Byte Selects

13.1SEL Signals 13.2Byte Enables 13.3Partial Writes 13.4Alignment 13.5Data Masking

Module 14

Block Transfers

14.1Sequential Transfers 14.2Throughput Improvements 14.3Burst-Like Behavior 14.4Memory Accesses

Module 15

Read-Modify-Write Cycles

15.1Atomic Operations 15.2Synchronization 15.3Shared Resources 15.4Multi-Master Systems

Module 16

Multi-Master Systems

16.1Why Multiple Masters Exist 16.2CPU + DMA Systems 16.3Bus Ownership 16.4Resource Sharing

Module 17

Arbitration

17.1Fixed Priority 17.2Round Robin 17.3Fairness 17.4Starvation 17.5Arbitration Logic

Module 18

Interconnect Design

18.1Shared Bus 18.2Crossbar Concepts 18.3Routing 18.4Scalability 18.5Open-Source SoC Examples

Module 19

Wishbone in RISC-V Systems

19.1RISC-V SoCs 19.2LiteX 19.3Open Hardware Systems 19.4CPU Integration 19.5Peripheral Integration

Module 20

Wishbone vs AXI

20.1Complexity Comparison 20.2Handshake Comparison 20.3Performance Comparison 20.4Learning Advantages 20.5Design Trade-offs

Module 21

Wishbone vs APB

21.1Simplicity 21.2Throughput 21.3Use Cases 21.4Integration Trade-offs

Module 22

Performance Analysis

22.1Throughput 22.2Latency 22.3Wait-State Impact 22.4Arbitration Cost 22.5Design Optimization

Module 23

Wishbone RTL Design

23.1Master Design 23.2Slave Design 23.3Register Bank Design 23.4Memory Controller Design 23.5Address Decoder RTL 23.6Interconnect RTL

Module 24

Wishbone Slave Design

24.1Register Maps 24.2Read Logic 24.3Write Logic 24.4ACK Generation 24.5Error Generation

Module 25

Wishbone DMA Design

25.1DMA Master 25.2Memory Transfers 25.3Peripheral Transfers 25.4Arbitration Impact

Module 26

Wishbone Verification

26.1Protocol Rules 26.2Assertions 26.3Monitors 26.4Scoreboards 26.5Coverage 26.6UVM Concepts

Module 27

Wishbone Debugging

27.1Missing ACK 27.2Wrong Address Decode 27.3Wait-State Bugs 27.4Arbitration Failures 27.5Data Corruption 27.6Waveform Analysis

Module 28

Interview Mastery

28.1Beginner Questions 28.2Intermediate Questions 28.3Advanced Questions 28.4Senior Questions

Module 29

Real Industry Case Studies

29.1FPGA SoCs 29.2LiteX Systems 29.3Open Hardware Projects 29.4Educational CPUs 29.5Research Platforms

Module 30

Wishbone Design Review Checklist

30.1RTL Checklist 30.2Verification Checklist 30.3Address Map Checklist 30.4Integration Checklist 30.5Debug Checklist 30.6Interview Checklist

Module 31

Wishbone Misconceptions Engineers Have

31.1"Wishbone Is Obsolete"31.2"Wishbone Cannot Scale"31.3"Wishbone Is Only for Hobby Projects"31.4"AXI Always Replaces Wishbone"31.5"ACK Must Assert Immediately"31.6"Wishbone Cannot Support DMA"