Advanced Questions

Everything so far has had one master and one slave. Add a second master and an interconnect and the questions change shape: they stop being about signals and start being about whose transfer this was, and about which layer of a verification environment is entitled to say anything.

1. Connecting Masters To Slaves

Q. How would you connect two masters to several slaves?

The structure is four jobs, and naming them separately is most of the answer:

Arbitrate, decode, route, return. The fourth is the one candidates skip, and it is the one that produces the worst bugs.

Q. What state must the interconnect preserve? Exactly one thing, and say it in these words: the association between a response and the master it belongs to, for as long as the phase is open. Everything else can be combinational. That association cannot, if ownership is allowed to change.

2. Grant Is Not Completion

Q. A master was granted the bus. What has it achieved?

Nothing yet. Grant means you may present. It does not mean presented, decoded, delivered, answered or returned. A DMA that advances a progress counter on grant is counting permission, not work — the same class of error as the driver that counts RTY as completion in Chapter 28.2.

Q. Can ownership change while a transfer is open?

It must not. RULE 3.25 makes CYC_O the marker for the whole cycle, so a fabric that re-arbitrates inside one has handed a master's transfer to somebody else. What makes it expensive is that every individual port stays protocol-shaped while it happens — the requests are legal, the terminations are legal, and the association between them is wrong.

3. Contention, Starvation, Corruption

These three words are not synonyms and an interviewer will find out whether you think they are.

  M0 requested clocks      30
  M0 owned clocks          30
  M1 requested clocks      32
  M1 owned clocks          12
  phases completed         12
  owner changed mid-phase  0
  response misdelivered    0
  M0 operations retired    6
  M1 operations retired    6
  protocol violations      P0 0   P2 0
  assertions   A1 0 A2 0 A3 0 A4 0 A5 0

That is a correct system. M1 asked for the bus on 32 clocks and owned it on 12; it waited for 20 clocks it did not get; and all six of its operations completed. Contention is not a failure — it is what a shared bus is.

Q. Does Wishbone mandate round-robin, or any fairness at all?

No. B3 mandates no arbitration algorithm. There is a recommendation that touches on it from an unexpected direction:

RECOMMENDATION 3.05 — Arbitration logic often uses CYC_I to select between MASTERs. Keeping CYC_O asserted may lead to arbitration problems.

Set beside PERMISSION 3.05 — "MASTER interfaces MAY assert CYC_O indefinitely" — that is a genuine tension the specification states and does not resolve. A master is permitted to hold the bus forever, and holding it may break your arbiter. Which is exactly right, because whether that matters is a system question.

It also tells you where starvation actually comes from. Chapter 27.4 armed a deliberately unfair arbiter and measured M1's ownership share at 28% — identical to the fair one — because the competing master released CYC_O between transfers. Starvation needs an owner that does not let go, not merely a priority order. If an interviewer asks you to fix starvation, ask first whether anybody is holding CYC_O.

4. Protocol-Clean And Functionally Wrong

Q. Can a request reach the wrong peripheral without violating anything?

Yes. This is the question most likely to separate candidates, because the correct answer is counter-intuitive until you have seen the numbers.

Four register operations, run on a correct system and on one where routing delivers them to the memory instead:

  op  address  control target  rig F target  control term  rig F term
   0  0x0000  S0 regs       S1 mem        ACK           ACK 
   1  0x0000  S0 regs       S1 mem        ACK           ACK 
   2  0x0006  S0 regs       S1 mem        ERR           ACK 
   3  0x0004  S0 regs       S1 mem        ACK           ACK 

  register slave phases presented  control 4   rig F 0
  register writes committed        control 1   rig F 0
  protocol violations              control 0   rig F 0
  immediate assertions SPEC        control 0   rig F 0
  immediate assertions LOCAL       control 0   rig F 0
  monitor transactions             control 4   rig F 4
  scoreboard mismatches            control 0   rig F 1
    of which data                  control 0   rig F 0
    of which termination           control 0   rig F 1

Read it in the order a debugger meets it.

Protocol violations: zero. Both boundaries, both rigs. Nothing illegal happened — delivering a request to the wrong slave is not illegal, it is merely wrong.

Monitor transactions: four in both. The observer reconstructed four transfers with the same addresses and directions. It is working perfectly and has nothing useful to say.

Register slave phases presented: zero. Four register operations acknowledged; the register bank never strobed once.

Scoreboard mismatches: one of four. Only the write to the read-only register at offset 6 fails, because the correct system refuses it with ERR and the memory — which has no notion of read-only — acknowledges. Three of the four wrong transfers produce no mismatch at all, because writing and reading the same wrong location is self-consistent.

5. DMA, And What Survives Losing The Bus

Q. A DMA has completed its source read. It loses arbitration before the destination write. What state must survive?

Work through it rather than listing:

• The read completed. Its data exists and is not on the bus any more. If the DMA has no holding register, the value is gone and the only recovery is to read it again — which is a different transaction, at a location that may have changed.
• Source progress may advance. That read really happened.
• Destination progress must not. Nothing was written.
• The transfer count must not advance, because a transfer is source-plus-destination, not one bus phase.
• The descriptor must be a snapshot, not a live read of memory that another master may be editing.
• Arbitration is independent of all of the above. Losing the bus is not an error and not a reason to restart anything.

Q. When should a DMA's progress counters advance? On the completion of the thing they count. A counter of bytes written advances when a write is acknowledged — not when the read finished, not on grant, and not on RTY.

Q. How should a DMA react to RTY? Re-present the same transfer. Advance nothing. And note the policy question hiding inside: how many times before it gives up is yours to decide, because B3 says when and how the cycle is retried is defined by the IP core supplier.

6. One Symptom, Two Cultures

Q. Your scoreboard reports one data mismatch. Is the DUT wrong?

No conclusion yet, and a candidate who reaches for the RTL here has told you how they spend their debug time.

Same program, same partial write over a seeded word, three rigs:

  rig        scoreboard  data  term  protocol P0  protocol P2
  control            0     0     0            0            0
  rig 1              1     1     0            0            0
  rig 2              1     1     0            0            0

  the lineage of the readback:
  rig      master mask  delivered mask  committed  bus data   model expected
  control           2               2  0xffffaaff 0xffffaaff 0xffffaaff
  rig 1             2               f  0x0000aa00 0x0000aa00 0xffffaaff
  rig 2             2               2  0xffffaaff 0xffffaaff 0x0000aa00

Rig 1 and rig 2 report the same count, of the same kind, on the same transfer. One is a design defect; the other is a reference model with the wrong byte-lane semantics on a design that did exactly what it was asked.

The line that separates them is the delivered mask. Rig 1 asked for 2 and the slave received f. Rig 2 asked for 2 and the slave received 2 — and the model is the thing holding a different opinion.

So the answer to "is the DUT wrong" is a method, not a verdict:

1. Is the committed state correct? A back-door read answers it.
2. Did the slave drive the right value? Its own DAT_O answers it.
3. Did the bus carry it? A raw-pin capture answers it.
4. Did the observer record it correctly?
5. Did the predictor expect the right thing?

Walk downwards and stop at the first disagreement. Two of the five possible answers are not in the design at all.

7. What Belongs Where

Q. What belongs in a monitor? What belongs in a scoreboard?

A clean division that survives follow-ups:

The monitor must be passive — an observer that can influence what it observes cannot be used to judge it. And it must make no prediction, because the moment it does, a disagreement between monitor and model becomes unattributable.

Q. Why is functional coverage not defect sensitivity?

Because a bin records that a situation occurred, not that the stimulus could have told the difference. Chapter 26.5 hit a partial-write bin with zero-filled data into a zero register: covered, and structurally incapable of detecting a lane defect. Coverage is a necessary condition for having tested something and never a sufficient one.

8. Debugging, Compressed

Three questions an interviewer will ask in sequence, and the shape of each answer.

Q. How do you debug a missing ACK? Not by opening the slave. A missing completion has about ten mechanisms and they live at five different boundaries. Establish whether the request was presented, granted, decoded, forwarded, terminated at the slave, and returned. Find the last good boundary and the first bad one. Chapter 27.1 built two defects that are identical at the master port and diverge at the same clock in different places.

Q. How do you localise data corruption? Record the value at every edge of the lineage — stimulus, master DAT_O, routed data and mask, committed storage, slave DAT_O, returned data, monitor record, model prediction — and find the earliest edge that disagrees. Do not start by accusing.

Q. How do you prove a fix? Six conditions, and "the test passes now" is only the fifth:

1. a mechanism that explains the symptom;
2. evidence that the mechanism actually occurred;
3. a first divergence consistent with it;
4. a correction that removes the divergence;
5. the original failing test passing;
6. a regression that failed before the fix and is clean after.

The sixth clause matters. A regression that passed before the fix proves nothing about the fix.

9. What To Carry Forward

• Arbitrate, decode, route, return. The fourth job is the one candidates skip and the one that misdelivers responses.
• Grant is permission, not progress.
• Contention is normal. Starvation needs an owner that holds CYC_O; the specification flags that tension itself.
• A wrong-target access can be perfectly conformant. Four ACKs, zero violations, zero register-slave phases.
• A scoreboard mismatch names a disagreement, not a culprit. Two of five candidate causes are outside the design.
• Monitors reconstruct, models predict, and neither may do the other's job.
• Coverage is necessary and never sufficient.
• A fix is proven by six things, one of which is a regression that used to fail.

Chapter 28.4 stops asking whether you know Wishbone and starts asking whether you can own a subsystem.