Beginner Questions

An interviewer asking "what is CYC_O?" is not checking whether you have read a datasheet. They are checking whether you have a model — something you can run in your head, predict with, and be wrong with in a specific way.

Interview mastery is reconstruction, not recall. A memorised answer survives exactly one follow-up question.

1. The Answer Ladder

Most Wishbone questions can be answered at six increasing depths. You do not always climb all six. You should always know which rung you stopped on.

At this level, rungs 1–3 are usually enough. What separates a good beginner answer from a weak one is almost never vocabulary — it is whether rung 2 distinguishes what Wishbone requires from what your system happens to do.

2. Explain Wishbone In Sixty Seconds

What the question tests: whether you can compress without lying.

A strong sixty seconds:

Wishbone is a synchronous point-to-point bus interface. A master drives an address, a direction, byte selects and — on a write — data, and asserts two qualifiers: CYC_O for the whole bus cycle and STB_O for the individual transfer. The slave answers every strobe with exactly one termination: ACK_O, or optionally ERR_O or RTY_O. Until it answers, the phase is open and the master holds the request still. There is no stall signal and no latency bound — a slave that needs time says so by not answering yet. Everything above one transfer — arbitration, address maps, timeouts, retry policy — is built on top by the integrator, not specified by the protocol.

That is rungs 1, 2 and 4 in one breath, and it ends by drawing the line the rest of the interview will test.

3. Draw It

You will be asked to draw this. It should take forty seconds and you should be able to say who drives each wire without looking.

The point of the drawing is not the wire list. It is that direction is ownership: a master never drives ACK, a slave never drives ADR, and nothing you build later may blur that.

4. CYC And STB — The Question Behind The Question

Q. What does CYC_O mean? What does STB_O mean? Why are they separate?

The first two are definitions. The third is the real question, and most candidates answer it with a slogan — "CYC is the whole cycle, STB is one transfer" — which is true and explains nothing.

The protocol reason is specific and checkable. B3 contains a permission:

PERMISSION 3.40 — If a MASTER doesn't generate wait states, then STB_O and CYC_O MAY be assigned the same signal.

Read that carefully. The specification says the two signals may be the same wire under a stated condition. So they are not separate because separation is intrinsically virtuous — they are separate because of what happens when the condition fails.

In a block cycle, CYC_O remains asserted across several transfers while the master may negate STB_O between them to insert its own wait states. That is the case PERMISSION 3.40 excludes, and it is the reason the two signals exist independently: CYC_O is a claim on the bus that spans transfers, STB_O is a claim on this transfer. A master that never throttles never needs the distinction. A master that does cannot live without it.

There is a second consequence, and it appears again in Chapter 28.3: arbitration commonly watches CYC_O, because that is the signal that means I still need the bus.

5. Terminations

Q. What completes a transfer? What is the difference between ACK, ERR and RTY?

One termination completes a phase. All three end it; they differ in what they say about the operation:

The two "supplier-defined" cells are not vagueness on my part — they are the specification's own words. For ERR_I: "The source of the error, and the response generated by the MASTER, is defined by the IP core supplier." For RTY_I: "When and how the cycle is retried is defined by the IP core supplier."

So an answer that says "on ERR the master aborts the burst" has described a system, not the protocol.

The conditional everyone drops

Q. Can a slave assert ACK_O and ERR_O at the same time?

The reflex answer cites RULE 3.45. Here is what it actually says:

RULE 3.45 — If a SLAVE supports ERR_O or RTY_O, it MUST NOT assert more than one of ACK_O / ERR_O / RTY_O at any time.

The antecedent is doing real work. A slave that implements only ACK_O is not governed by the rule at all, because there is nothing for ACK_O to be exclusive with. Reciting the rule without its condition is the most common way to be technically wrong while sounding well-prepared — and an interviewer who knows the specification will ask exactly this.

6. Waiting

Q. Can ACK be delayed? By how much?

Yes, and there is no bound. The specification's own description of a read says the slave "may insert wait states before asserting ACK_I, thereby allowing it to throttle the cycle speed", and of a write that "any number of wait states may be added."

There is no stall signal in Wishbone Classic. Waiting is expressed by one thing only: withholding the termination.

Q. Is a timeout part of Wishbone?

No — and this one is worth getting exactly right, because the specification does mention timeouts:

RECOMMENDATION 3.10 — Design INTERCON modules to prevent deadlock. One solution is a watchdog timer function that monitors the MASTER's STB_O signal.

A recommendation about a system component. Not a rule, not a protocol signal, not a required behaviour. If your design has a deadline, it comes from your requirements document. The honest sentence in a bug report is "the phase has been open for N observed clocks", never "the slave violated the specification". Chapter 27.1 measured a rig where that distinction was the whole diagnosis.

Q. What must remain stable while waiting?

RULE 3.60 — The MASTER MUST qualify the following signals with STB_O: ADR_O, DAT_O(), SEL_O(), WE_O, TAGN_O.

Rung 4, the consequence: an open phase represents one request. If the address, the write data, the byte lanes or the direction change while that phase is still open, the termination that eventually arrives belongs to a different request than the one that was asked. The slave has no way to know which.

7. Two Waveform Predictions

These come from an executable lab. Work them out before reading on.

Two rigs, the same slave, the same four operations — a full-word write to word 1, a read back, a single-lane write, a read back. The only difference is the slave's wait-state count: zero in one, two in the other.

Measured:

  rig            transfers  wait clocks  acks  completion cycles
  WAITS=0 comb          4            0     4   2 7 12 17
  WAITS=2 comb          4            8     4   4 11 18 25

  word 1 after the run   WAITS=0 0xa1b2bbd4   WAITS=2 0xa1b2bbd4
  commits                WAITS=0 2          WAITS=2 2

Note the third column of the completion cycles: the gap between consecutive completions is 5 clocks in one rig and 7 in the other, and the number of commits is 2 in both. Two writes, two commits. Hold onto that — Chapter 28.2 breaks it on purpose.

8. The RTL Question

Almost every beginner Wishbone interview ends with "write me a minimal slave." Here is the one this module uses, in the two lines that carry all the reasoning:

  // RULE 3.30: a SLAVE may not respond to SLAVE signals when CYC_I is
  // negated. One gate, applied once, and every other expression below
  // depends on it.
  logic present;
  assign present = cyc_i && stb_i;

  // THE COMMIT QUALIFIER. This one line is the difference between a
  // correct slave and Lab B's broken one.
  logic commit;
  assign commit = WRITE_ON_STB ? (present && we_i) : (ack_o && we_i);

Three things an interviewer is listening for, none of which is syntax:

1. The CYC_I gate exists and is applied once. RULE 3.30 says a slave may not respond to slave signals while CYC_I is negated. Putting that gate in one place means no downstream logic has to remember it.
2. The commit is qualified by the termination, not by the strobe. ack_o && we_i, never stb_i && we_i. At zero wait states those are the same clock, which is exactly why the wrong one survives so long.
3. The read data is qualified too. RULE 3.65 requires the slave to qualify DAT_O() with its termination; driving it unconditionally is legal-looking and hides a class of timing bug.

If you can write those three lines and say why for each, you can write the rest of the slave at the whiteboard in a minute.

9. Does ACK Mean It Worked?

Q. The transfer was acknowledged. Was the operation correct?

No, and this is the single most useful thing on this page. ACK is a statement about the handshake: a request was presented and a slave answered it. It says nothing about which slave, which location inside it, or whether the right bytes moved.

Chapter 28.3 runs a rig where four register operations are acknowledged, zero protocol violations are reported, and the register bank is never strobed once. Keep the sentence:

Protocol conformance is not functional correctness.

10. What To Carry Forward

• Answer on a rung and know which one. Most beginner questions want 1–3; every one of them is improved by rung 2 being explicit about protocol versus policy.
• Direction is ownership. If you can draw the interface with the arrows right, half the follow-ups answer themselves.
• CYC_O and STB_O may legally be the same wire — under a stated condition. Knowing the condition is knowing why they are two signals.
• RULE 3.45 has an antecedent. A slave without ERR_O or RTY_O is outside it.
• Waiting is unbounded and legal. Timeout is RECOMMENDATION 3.10, about an interconnect, not a protocol rule.
• Commit on the termination, never on the strobe. At zero waits they coincide, which is why the wrong one ships.
• ACK is about the handshake. Nothing else.

Chapter 28.2 moves from describing signals to predicting what a given piece of RTL will actually do.