Burst-Like Behavior

Chapter 14.2 measured four transfers under one cycle, with addresses that incremented.

Nothing so far has said they had to.

If the slave is never told the length, the order, or when the block ends — in what sense is this a burst?

1. The Master Owns the Sequence

The specification's BLOCK READ walkthrough says the same thing at every phase boundary:

CLOCK EDGE 1: MASTER latches data on DAT_I(). MASTER presents new ADR_O() and TGA_O().

"New." Not incremented, not next, not sequential. The master presents an address and the slave decodes it, exactly as in a single cycle.

Nothing in Chapter 3 requires block phase addresses to be related to one another. The only occurrence of "sequential" in the whole chapter is RECOMMENDATION 3.20, and it is about something else: ordering the parts of one operand that has been split across several cycles, low address first. It says nothing about which addresses a block may visit.

So adr_q + STRIDE in Chapter 14.1's master is that master implementing a stream. It is LOCAL MASTER POLICY, and Section 4 replaces it.

2. Simulation — SIM E: A Sequential Block

The baseline, and the units are the point.

  === SIM E - a sequential block, in WORD units ===
    base word address 8, stride 1, four phases, one cycle.

    phase   ADR (word)   byte address   DAT        term
      0     0x00000008   0x00000020     0xa5000000 ACK
      1     0x00000009   0x00000024     0xa5000001 ACK
      2     0x0000000a   0x00000028     0xa5000002 ACK
      3     0x0000000b   0x0000002c     0xa5000003 ACK

    bus cycles 1   phases 4   ACKs 4

    ADR advances by ONE per phase because ADR is a WORD
    address on this port - Chapter 4.3 and Module 12. The byte
    column advances by four. Both describe the same step.

Reading it

ADR advances by one; the byte column advances by four. Both describe the same step, because ADR is a word address on this port — the specification's own example for a 32-bit byte-granular port is ADR_O(n..2), and Chapter 4.3 and Module 12 have used that convention throughout.

A block master that incremented by 4 would skip three words per phase. The transfers would all be legal and the data would land in the wrong places — the shape of defect Chapter 12.5 measured, arriving here through a stride instead of a decoder.

One cycle, four phases, four ACKs. Nothing here distinguishes this from Section 4 except the numbers in the ADR column.

3. What the Slave Sees

Exactly the same thing in both runs: a qualified transfer.

It has no beat index, because nothing sends one. It has no length, because there is no length on the bus. It cannot tell phase 3 of 4 from phase 3 of 400, and it cannot tell either from an unrelated single cycle that happens to follow another.

The one thing it could look at is CYC_I — and most slaves do not, for this purpose. The RAM in Chapter 14.1 gates on CYC_I && STB_I for qualification and never asks whether CYC_I was already high.

Which is why Chapter 8.3's observation holds: a correct single-transfer slave already supports block cycles. There is nothing to add. PERMISSION 3.55 even allows an interface to be designed so that it does not support BLOCK cycles — a statement that only makes sense because supporting them is, for most slaves, doing nothing in particular.

4. Simulation — SIM F: A Block That Is Not a Sequence

The same master, the same RAM, one cycle, four phases. The address for each phase comes from a list instead of from a counter.

  === SIM F - a block whose addresses are not sequential ===
    the same master, the same RAM, one cycle, four phases.
    the address for each phase comes from a list instead of
    from a counter.

    phase   ADR (word)   step from previous
      0     0x00000008       -
      1     0x0000000c      +4
      2     0x00000009      -3
      3     0x0000000f      +6

    bus cycles 1   phases 4   ACKs 4   RAM writes 4

    Forward four, back three, forward six - inside ONE block
    cycle, every phase acknowledged, nothing refused.

    NOTHING IN THE CLASSIC PROFILE REQUIRES BLOCK ADDRESSES TO
    BE SEQUENTIAL. The specification says the master 'presents
    new [ADR_O()]' for each phase - new, not incremented. The
    only sequencing statement in the chapter is RECOMMENDATION
    3.20, and that is about ordering ONE operand split across
    cycles, not about block addressing.

    So the counter in SIM E is MASTER POLICY implementing a
    stream. It is not a protocol mechanism, and the slave
    cannot tell the two runs apart from any one phase.

Reading it

Forward four, back three, forward six — inside one block cycle, every phase acknowledged, nothing refused.

The cycle count is 1 and the ACK count is 4, identical to SIM E. The slave answered a scattered set of addresses exactly as it answered a consecutive one, because from its side there was no difference to notice.

This is what separates a block from an incrementing burst. A burst protocol that declared "four beats, incrementing" would have made this sequence inexpressible. Classic Wishbone declares nothing, so there is nothing for this sequence to contradict.

The honest statement about legality is narrow, and worth making as the narrow one. The specification does not forbid non-sequential block addresses — no rule constrains the relationship between phase addresses, and the text says only that the master presents a new one. That is permission by absence, which is weaker than an explicit blessing and should be said that way.

What is a real question is whether it is a good idea. A scattered block still holds the resource for its whole duration, and a memory that could have exploited locality cannot. Legal and sensible are different tests, and only the first one is the specification's business.

5. The Vocabulary, Kept Apart

Each of these means something different, and importing the wrong one predicts behaviour that does not exist.

Two of these are absent from Classic entirely, and both are words engineers reach for first.

The practical test for which word applies: ask what the slave was told. Told a length and a pattern → burst. Told nothing but a qualified transfer → block. Ask whether a second request can be issued before the first is answered. Yes → pipelined. No → back-to-back at best.

6. Failure Modes and Discriminating Evidence

Symptom: a slave prefetches the wrong data during a block.

Candidate causes. The slave assumed a sequential access pattern that the master did not promise.

Discriminating evidence. The address sequence at the phase boundaries. If it is non-sequential and the slave prefetched, the slave inferred something it was never told. SIM F is legal traffic, and a slave that misbehaves on it has a defect regardless of how unusual the pattern is.

Symptom: block addresses land four words apart.

Candidate causes. A stride of 4 on a word-addressed port.

Discriminating evidence. The gap between consecutive ADR values. Exactly 4 with every fourth word written is a units error, not a logic error — the transfers are all legal and all in the wrong place.

Symptom: an integration works with one master and fails with another, on the same slave.

Candidate causes. The failing master issues non-sequential or long blocks the slave was silently tuned for.

Discriminating evidence. Whether the slave's behaviour depends on CYC_I history. A slave whose response changes because CYC_I was already high is inferring block structure. It is entitled to look at CYC_I; it is not entitled to be wrong when the pattern differs.

Symptom: a design expects latency to be hidden across a block and it is not.

Candidate causes. A pipelining assumption applied to Classic.

Discriminating evidence. Whether any phase is presented before the previous one is answered. In Classic, never. The total is the sum of the phases' latencies, which Chapter 14.2's latency column measures directly.

7. Verification

The properties in Chapter 14.1 Section 9 cover this chapter, and P7 is the one that matters here.

p_sequential_progression is true of SIM E's master and false of SIM F's, and both are conformant. That is why the property carries its scope in its comment rather than in a reader's memory.

A checker that asserted sequential progression as a protocol property would fail SIM F — and the temptation would then be to call SIM F illegal rather than to notice the property was aimed at a policy.

What is checkable across both is everything the profile does constrain: CYC_O spanning STB_O (P1, RULE 3.25), the payload qualified by STB_O (P2, RULE 3.60), one termination per phase, and the count matching the request. SIM F satisfies all of them.

8. Common Mistakes

"Block transfer and burst are synonyms."

Wrong mental model: one concept, two names.

What is true: a burst declares its shape; a Classic block declares nothing. B3 does have burst metadata — CTI_O() and BTE_O() — and it is in the Registered Feedback profile, not this one.

"Keeping CYC_O high increments the address."

Wrong mental model: the protocol tracks a stream.

What is true: the master drives every address. The specification says it presents a new one each phase, and SIM F presents four that are not a sequence.

"A block must be sequential."

Wrong mental model: the block type implies an order.

What is true: nothing in Chapter 3 constrains the relationship between phase addresses. The one "sequential" in the chapter is RECOMMENDATION 3.20, about splitting one operand across cycles.

"The slave knows the burst length."

Wrong mental model: the cycle carries a count.

What is true: there is no length on the bus. The slave learns the block has ended when CYC_O falls, which is after the last phase, not before it.

"Classic Wishbone is pipelined because it can do a word per clock."

Wrong mental model: rate implies structure.

What is true: one transfer is outstanding at a time. A word per clock is the ceiling of a back-to-back non-pipelined bus, and Classic reaches it — that is not the same as overlapping requests.

"A TGC_O() cycle tag tells the slave the block's shape."

Wrong mental model: the tag is metadata.

What is true: RECOMMENDATION 3.15 is advisory and identifies the cycle type — SGL_O, BLK_O, RMW_O. It carries no length and no address pattern.

9. Interview Reasoning

10. Understanding Check

11. What's Next

The vocabulary is settled: a block is a grouping, a burst declares its shape, and the profile that carries burst metadata is a different chapter of the same specification.

Every block so far has written to a memory that answered instantly, or at one fixed speed.

What does a block transfer look like against memory that responds at a different speed each time — and what happens when the master counts its own transfers wrong?

Chapter 14.4 — Memory Accesses writes and reads a block against a reference model, gives each phase a different latency, and measures a master that performs one transfer too many. The full path is on the Wishbone curriculum index.