Waveform Analysis

Every chapter so far explained a mechanism and then showed a waveform of it. This one reverses the direction: here is a trace, and nobody has told you what it does.

How do you read an arbitrary Wishbone read off a waveform, and localise a failure from evidence alone?

1. The Nine-Step Method

Step 4 carries the discipline that makes the rest work. ADR_O is only meaningful while STB_O qualifies it (RULE 3.60), so reading it from an unqualified cycle is reading residue. Always name which of Chapter 6.2's three representations you are looking at — byte offset, global word address, or local offset — because the same location has three different values.

Step 8 is the one most often skipped, and it is the only step that separates a slave fault from a master fault when both produce a wrong value.

2. Trace A — A Correct Read

Walking the method:

1–2. CYC_O asserted cycles 2–4; STB_O asserted across the same interval and never outside it. One transfer.

3. WE_O negated throughout. A read, and it stayed a read — RULE 3.60's stability holding.

4. ADR_O reads 0x4 in all three qualified cycles. One value, no drift. That is the global word address; in the running map it is also local offset 4, and a datasheet would call it byte offset 0x10.

5. sel[0] asserted for exactly the presented interval. One target, and the right one.

6. ACK_I in cycle 4 only. No ERR_I, no RTY_I. Cycles 2 and 3 are wait states — the slave throttling by withholding, per Chapter 6.5.

7. DAT_I is 0x0 in cycles 2–3 and carries the value in cycle 4 — exactly coincident with the termination, which is RULE 3.65 satisfied.

8. rdat changes at the edge ending cycle 4, taking the value that was on DAT_I in that cycle. The capture edge and the termination edge are the same edge.

9. Both qualifiers negate in cycle 5, one done pulse, and the bus is idle.

Every step consistent. This is the shape the four broken traces should be compared against.

3. Trace B — Nothing Ever Terminates

Steps 1–4 are clean. A cycle exists, a transfer is presented, it is a read, and the address is stable at word 7.

Step 6 is where it stops: no termination, ever.

The method has narrowed it to stages 3–6 of the read path, and no further — because this master-side trace is identical for all four candidates. Step 5 is what separates them, and it needs signals this trace does not contain.

The one reading that is not a hang: if ACK_I were asserted while the master sat still, that is a RULE 3.55 violation — the master edge-detecting a legally-held acknowledge (Chapter 5.4). Trace B shows ACK_I low, so that is excluded.

The address is the clue worth acting on. Word 7 is outside the running peripheral's five registers. Chapter 6.2 §11 showed an unmapped address hanging when there is no default responder — and RECOMMENDATION 3.10 puts the watchdog in the interconnect for exactly this.

4. Trace C — The Address Moved

Steps 1–3 pass. Steps 6, 7, 8 and 9 also pass — there is one clean termination, the data is valid exactly in that cycle, the capture is on the right edge, and the master releases properly.

Only step 4 fails, and it fails in a way that is easy to skim past: ADR_O shows three different values across three qualified cycles. RULE 3.60 qualifies the address with STB_O, so it must hold still for the transfer's whole duration.

Why every other step looks fine. The slave answered the address it saw. The data is genuinely the contents of whatever register that was. Nothing downstream of the address is wrong — which is exactly why a debugger starting at the data finds nothing.

Distinguishing the two causes (Chapter 6.2 §7): if ADR_O tracks the client's request input it is an unlatched master (Chapter 5.5); if it diverges from both the client and the original request — as here, incrementing — it is being rewritten internally.

The severity depends on the map. Here the drift landed on word 5, but had the map been denser it would have landed on an implemented register and returned a plausible wrong value with ACK — which Chapter 6.4 §6 measured.

5. Trace D — ACK With the Wrong Data

All nine steps pass. The address is stable, the termination is single and clean, the data is valid exactly in the termination cycle, the capture edge is correct, the master releases.

And the value is wrong — 0x57420601 is ID at word 4, not INPUT_DATA at word 3.

This is the trace that proves the method has a boundary. The nine steps verify that the protocol was obeyed. They cannot verify that the right register was read, because the bus carries no information about what word 3 should contain.

Four candidates remain, and the waveform separates none of them:

All four are internal signals. Step 5 in a richer trace — with per-slave selects and offsets captured — would eliminate the third and fourth immediately, which is the argument for instrumenting the interconnect rather than only the endpoints.

6. Trace E — Captured Before the Answer

Steps 1–7 all pass. In particular step 7 passes: DAT_I is valid exactly in the termination cycle, so the slave is behaving perfectly.

Step 8 is the failure, and it is only visible because the capture strobe is in the trace. The master sampled in cycles 2 and 3 — while the read was outstanding and no termination had arrived — and did not sample in cycle 4.

Without the capture strobe this trace is nearly unreadable. rdat holds zero and done asserts; the bus is conformant throughout. Chapter 6.3 §6 noted that early and late capture produce the same result, and the strobe is what distinguishes them.

Why "every read returns zero, address-independent" is the field symptom. A capture-edge fault affects all reads equally, unlike a mux or decode fault which varies with address. Chapter 6.3 §5 tabulated that discriminator.

7. The Decision Tree

The rightmost branch is the important one, and it is the lesson of Trace D. A trace on which all nine steps pass has told you everything a bus-level view can tell you. Whatever remains is internal state, and no amount of further staring at the same signals will produce it.

What to add to the trace at that point, in order of usefulness: the slave's local offset, the per-slave select vector, the slave's read-multiplexer output, the master's capture strobe, and — for a registered slave — its remembered offset. Those five signals resolve every failure in Module 6.

8. Failure Modes and Discriminating Evidence

Symptom: a read hangs.

Candidate causes. Decode selected nobody; decode selected the wrong slave; the slave has an unterminated path; the return path drops the termination; the master lacks the termination input the slave produced.

Discriminating evidence. Trace B's probe table. The first probe at which the expected signal is absent names the stage, and the master-side view names none of them.

Property. A bounded-completion check, which Chapter 5.8 §9 classified as system policy rather than a Wishbone rule — RECOMMENDATION 3.10 puts it in the interconnect.

Symptom: a read completes with the wrong value, and the address on the bus was stable.

Candidate causes. Mux arm, lost context, wrong local offset, or a polluted merge.

Discriminating evidence. Trace D's table. Address-dependence splits it first: one offset wrong points into the slave, all offsets wrong points at the merge or the capture.

Symptom: every read returns zero regardless of address.

Candidate causes. Capture outside the termination cycle.

Discriminating evidence. The capture strobe against ACK_I (Trace E). Address-independence is the signature; the strobe separates early from late.

Property. $changed(rdat_q) |-> $past(cyc_o && stb_o && ack_i && !we_o).

Symptom: ACK_I is asserted and the master makes no progress.

Candidate causes. The master is edge-detecting a legally-held acknowledge.

Discriminating evidence. This is the one hang-like picture where ACK_I is high rather than low — a RULE 3.55 violation in the master, measured in Chapter 5.4 §7.

Symptom: reads are correct but a peripheral loses events.

Candidate causes. A side effect gated on presentation rather than acceptance.

Discriminating evidence. Not visible on any waveform of the bus. Count side effects against completed reads (Chapter 6.5 §6).

9. What a Waveform Cannot Tell You

Worth stating plainly, because the method's value depends on knowing its edge.

A bus trace can establish: that the protocol was obeyed; which address was presented; when data was valid; when the master captured; whether the transfer terminated and how.

A bus trace cannot establish: whether the right register was read; whether a side effect fired the right number of times; whether a registered slave answered from the right context; whether internal state is correct.

Traces D and E are the two halves of this. D is fully conformant and functionally wrong. E is fully conformant on the bus and only diagnosable because a non-bus signal was in the trace.

This is the same boundary Module 5 reached repeatedly — lost atomicity, repeated side effects, the RULE 3.55 stall — and which Chapter 5.8 §8 collected: conformance is necessary, finite, and not sufficient. The nine steps verify conformance. Everything beyond needs internal signals, assertions with white-box access, or a system-level test that checks outcomes rather than wires.

10. Common Mistakes

"The data was on the bus, so the slave is fine."

Wrong mental model: presence proves correctness.

Concrete bug: concluding a slave is innocent in Trace D, where the data was genuinely present and genuinely the wrong register's.

Observable evidence: a conformant trace and a wrong value.

Correct model: step 7 checks when data was valid, not what it was. The bus carries no expectation to compare against.

"Read ADR_O to see what was accessed."

Wrong mental model: the address bus always says the address.

Concrete bug: reading ADR_O from an unqualified cycle and diagnosing the wrong target.

Observable evidence: an address that "does not match" the software, because it is residue from an earlier transfer.

Correct model: RULE 3.60 makes ADR_O meaningful only under STB_O. Step 4 says while qualified for this reason.

"No ACK means the slave failed."

Wrong mental model: the last stage is the guilty one.

Concrete bug: opening a slave's RTL for Trace B, where three of the four candidates are outside it — including the master violating RULE 3.25 (Chapter 5.2).

Observable evidence: a slave that is behaving perfectly.

Correct model: probe forward along the path. The first absence names the stage.

11. Interview Reasoning

12. Understanding Check

13. Module 6 Complete

A Wishbone read is now fully traced, implemented, verified and diagnosable.

What Module 6 deliberately did not do. It used one basic read throughout and left the wider subjects alone: Module 8 owns block and read-modify-write cycles, Module 9 wait-state generation and performance, Module 10 error handling, Module 11 retry, Module 12 address decoding, Module 13 byte selects.

The mirror-image question is next, and it differs in one decisive respect. On a read, the master asks and the slave supplies the data — a wrong answer corrupts only the master's copy. On a write, the master supplies data that changes the slave's state, and a mistake is committed into the device rather than returned to the requester.

What happens, end to end, in a single Wishbone write cycle?

Module 7 — Write Transactions answers it, beginning with Write Cycle Flow. The full path is on the Wishbone curriculum index.