CPU + DMA Systems

// ─────────────────────────────────────────────────────────────────────────
// m16_system — the one system Module 16 uses, from 16.1 to 16.4.
//
//   CPU master ─┐                      ┌─ shared RAM      0x000..0x0FF
//               ├─ wb_owner_mux2 ─ wb_split2
//   DMA master ─┘                      └─ DMA config regs 0x800..0x803
//
// and, when WITH_PRIVATE is set, a second wb_split2 on the CPU's own port:
//
//   CPU master ─ wb_split2 ─┬─ to wb_owner_mux2   (shared, adr[10] = 0)
//                           └─ private RAM        (local,  adr[10] = 1)
//
// The private leg never reaches the interconnect, so a CPU access to it
// acquires no ownership and contends with nothing. That is Chapter 16.4's
// measurement and the reason the same splitter appears twice.
//
// WORD ADDRESSES throughout - adr[11:0] selects a 32-bit word, never a
// byte. adr[11] chooses RAM versus DMA registers; adr[10] chooses shared
// versus private.
//
// The defect parameters pass straight through to wb_owner_mux2 and are all
// off by default.
// ─────────────────────────────────────────────────────────────────────────
module m16_system #(
  parameter int unsigned AW               = 12,
  parameter int unsigned DW               = 32,
  parameter int unsigned SW               = DW/8,
  parameter int unsigned RAM_WAITS        = 0,
  parameter bit          RELEASE_ON_IDLE  = 1'b0,
  parameter bit          HONOUR_LOCK      = 1'b1,
  parameter bit          PREEMPT          = 1'b0,
  parameter bit          MIX_CONTEXT      = 1'b0,
  parameter bit          BROADCAST_RETURN = 1'b0,
  parameter bit          WITH_PRIVATE     = 1'b0
) (
  input  logic          clk_i,
  input  logic          rst_i,
  // CPU client contract - LOCAL, not Wishbone
  input  logic          cpu_req_i,
  input  logic          cpu_we_i,
  input  logic [AW-1:0] cpu_adr_i,
  input  logic [DW-1:0] cpu_dat_i,
  input  logic [SW-1:0] cpu_sel_i,
  input  logic          cpu_lock_i,
  input  logic          cpu_hold_i,
  output logic          cpu_busy_o,
  output logic          cpu_done_o,
  output logic          cpu_ok_o,
  output logic          cpu_xerr_o,
  output logic          cpu_xrty_o,
  output logic [DW-1:0] cpu_rdat_o,
  // shared RAM "local resource busy" input - answers RTY while asserted
  input  logic          ram_busy_i,
  // DMA observation
  output logic          dma_busy_o,
  output logic          dma_done_o,
  output logic          dma_failed_o,
  output logic [15:0]   dma_words_o,
  // resource observation
  output logic [15:0]   ram_writes_o,
  output logic [15:0]   priv_writes_o,
  // CPU master port (for the probe)
  output logic          cpu_cyc_o,
  output logic          cpu_stb_o,
  output logic          cpu_mwe_o,
  output logic [AW-1:0] cpu_madr_o,
  output logic [DW-1:0] cpu_mdat_o,
  output logic [SW-1:0] cpu_msel_o,
  output logic          cpu_ack_o,
  output logic          cpu_err_o,
  output logic          cpu_rty_o,
  // CPU port AS THE INTERCONNECT SEES IT. With WITH_PRIVATE set these are
  // the shared leg of the CPU's own splitter, and they differ from the
  // master's own pins on every private access. An instrument wired to the
  // master's pins instead reports contention that does not exist.
  output logic          cpu_icyc_o,
  output logic          cpu_istb_o,
  output logic          cpu_iwe_o,
  output logic [AW-1:0] cpu_iadr_o,
  output logic [DW-1:0] cpu_idat_o,
  output logic [SW-1:0] cpu_isel_o,
  output logic          cpu_iack_o,
  output logic          cpu_ierr_o,
  output logic          cpu_irty_o,
  // DMA master port (for the probe)
  output logic          dma_cyc_o,
  output logic          dma_stb_o,
  output logic          dma_mwe_o,
  output logic [AW-1:0] dma_madr_o,
  output logic [DW-1:0] dma_mdat_o,
  output logic [SW-1:0] dma_msel_o,
  output logic          dma_ack_o,
  output logic          dma_err_o,
  output logic          dma_rty_o,
  // shared downstream path (for the probe)
  output logic          s_cyc_o,
  output logic          s_stb_o,
  output logic          s_we_o,
  output logic [AW-1:0] s_adr_o,
  output logic [DW-1:0] s_dat_o,
  output logic [SW-1:0] s_sel_o,
  output logic [DW-1:0] s_rdat_o,
  output logic          s_ack_o,
  output logic          s_err_o,
  output logic          s_rty_o,
  output logic [1:0]    owner_o,
  output logic          s_lock_o
);
  // ── CPU master ──
  logic          c_cyc, c_stb, c_lock, c_we;
  logic [AW-1:0] c_adr;
  logic [DW-1:0] c_dat, c_rdat;
  logic [SW-1:0] c_sel;
  logic          c_ack, c_err, c_rty;

  wb_cpu_master #(.AW(AW), .DW(DW), .SW(SW)) u_cpu (
    .clk_i(clk_i), .rst_i(rst_i),
    .req_i(cpu_req_i), .req_we_i(cpu_we_i), .req_adr_i(cpu_adr_i),
    .req_dat_i(cpu_dat_i), .req_sel_i(cpu_sel_i), .req_lock_i(cpu_lock_i),
    .hold_i(cpu_hold_i),
    .busy_o(cpu_busy_o), .done_o(cpu_done_o), .ok_o(cpu_ok_o),
    .err_o(cpu_xerr_o), .rty_o(cpu_xrty_o), .rdat_o(cpu_rdat_o),
    .cyc_o(c_cyc), .stb_o(c_stb), .lock_o(c_lock), .we_o(c_we),
    .adr_o(c_adr), .dat_o(c_dat), .sel_o(c_sel),
    .dat_i(c_rdat), .ack_i(c_ack), .err_i(c_err), .rty_i(c_rty));

  assign cpu_cyc_o = c_cyc; assign cpu_stb_o = c_stb;
  assign cpu_mwe_o = c_we;  assign cpu_madr_o = c_adr;
  assign cpu_mdat_o = c_dat; assign cpu_msel_o = c_sel;
  assign cpu_ack_o = c_ack; assign cpu_err_o = c_err; assign cpu_rty_o = c_rty;

  // ── optional CPU-side local split ──
  logic          x_cyc, x_stb, x_lock, x_we;
  logic [AW-1:0] x_adr;
  logic [DW-1:0] x_dat, x_rdat;
  logic [SW-1:0] x_sel;
  logic          x_ack, x_err, x_rty;

  logic          p_cyc, p_stb, p_we;
  logic [AW-1:0] p_adr;
  logic [DW-1:0] p_dat, p_rdat;
  logic [SW-1:0] p_sel;
  logic          p_ack;

  generate
    if (WITH_PRIVATE) begin : g_priv
      wb_split2 #(.AW(AW), .DW(DW), .SW(SW), .SEL_BIT(10)) u_cpusplit (
        .m_cyc_i(c_cyc), .m_stb_i(c_stb), .m_lock_i(c_lock), .m_we_i(c_we),
        .m_adr_i(c_adr), .m_dat_i(c_dat), .m_sel_i(c_sel),
        .m_dat_o(c_rdat), .m_ack_o(c_ack), .m_err_o(c_err), .m_rty_o(c_rty),
        .a_cyc_o(x_cyc), .a_stb_o(x_stb), .a_lock_o(x_lock), .a_we_o(x_we),
        .a_adr_o(x_adr), .a_dat_o(x_dat), .a_sel_o(x_sel),
        .a_dat_i(x_rdat), .a_ack_i(x_ack), .a_err_i(x_err), .a_rty_i(x_rty),
        .b_cyc_o(p_cyc), .b_stb_o(p_stb), .b_lock_o(), .b_we_o(p_we),
        .b_adr_o(p_adr), .b_dat_o(p_dat), .b_sel_o(p_sel),
        .b_dat_i(p_rdat), .b_ack_i(p_ack), .b_err_i(1'b0), .b_rty_i(1'b0),
        .hit_b_o());
      wb_shared_ram #(.AW(AW), .DW(DW), .SW(SW), .WORDS(16), .WAITS(0))
        u_priv (.clk_i(clk_i), .rst_i(rst_i), .cyc_i(p_cyc), .stb_i(p_stb),
                .we_i(p_we), .adr_i(p_adr), .dat_i(p_dat), .sel_i(p_sel),
                .busy_i(1'b0), .dat_o(p_rdat), .ack_o(p_ack),
                .err_o(), .rty_o(), .writes_o(priv_writes_o));
    end else begin : g_nopriv
      assign x_cyc = c_cyc; assign x_stb = c_stb; assign x_lock = c_lock;
      assign x_we  = c_we;  assign x_adr = c_adr; assign x_dat = c_dat;
      assign x_sel = c_sel;
      assign c_rdat = x_rdat; assign c_ack = x_ack;
      assign c_err  = x_err;  assign c_rty = x_rty;
      assign priv_writes_o = 16'd0;
    end
  endgenerate

  assign cpu_icyc_o = x_cyc; assign cpu_istb_o = x_stb;
  assign cpu_iwe_o  = x_we;  assign cpu_iadr_o = x_adr;
  assign cpu_idat_o = x_dat; assign cpu_isel_o = x_sel;
  assign cpu_iack_o = x_ack; assign cpu_ierr_o = x_err;
  assign cpu_irty_o = x_rty;

  // ── DMA ──
  logic          d_cyc, d_stb, d_lock, d_we;
  logic [AW-1:0] d_adr;
  logic [DW-1:0] d_dat, d_rdat;
  logic [SW-1:0] d_sel;
  logic          d_ack, d_err, d_rty;

  logic          cfg_cyc, cfg_stb, cfg_we;
  logic [AW-1:0] cfg_adr;
  logic [DW-1:0] cfg_dat, cfg_rdat;
  logic          cfg_ack, cfg_err;

  wb_teaching_dma #(.AW(AW), .DW(DW), .SW(SW)) u_dma (
    .clk_i(clk_i), .rst_i(rst_i),
    .c_cyc_i(cfg_cyc), .c_stb_i(cfg_stb), .c_we_i(cfg_we),
    .c_adr_i(cfg_adr[1:0]), .c_dat_i(cfg_dat),
    .c_dat_o(cfg_rdat), .c_ack_o(cfg_ack), .c_err_o(cfg_err),
    .cyc_o(d_cyc), .stb_o(d_stb), .lock_o(d_lock), .we_o(d_we),
    .adr_o(d_adr), .dat_o(d_dat), .sel_o(d_sel),
    .dat_i(d_rdat), .ack_i(d_ack), .err_i(d_err), .rty_i(d_rty),
    .busy_o(dma_busy_o), .done_o(dma_done_o), .failed_o(dma_failed_o),
    .words_done_o(dma_words_o));

  assign dma_cyc_o = d_cyc; assign dma_stb_o = d_stb;
  assign dma_mwe_o = d_we;  assign dma_madr_o = d_adr;
  assign dma_mdat_o = d_dat; assign dma_msel_o = d_sel;
  assign dma_ack_o = d_ack; assign dma_err_o = d_err; assign dma_rty_o = d_rty;

  // ── the interconnect ──
  logic          s_cyc, s_stb, s_lock, s_we;
  logic [AW-1:0] s_adr;
  logic [DW-1:0] s_dat, s_rdat;
  logic [SW-1:0] s_sel;
  logic          s_ack, s_err, s_rty;

  wb_owner_mux2 #(
    .AW(AW), .DW(DW), .SW(SW),
    .RELEASE_ON_IDLE(RELEASE_ON_IDLE), .HONOUR_LOCK(HONOUR_LOCK),
    .PREEMPT(PREEMPT), .MIX_CONTEXT(MIX_CONTEXT),
    .BROADCAST_RETURN(BROADCAST_RETURN)
  ) u_mux (
    .clk_i(clk_i), .rst_i(rst_i),
    .cpu_cyc_i(x_cyc), .cpu_stb_i(x_stb), .cpu_lock_i(x_lock),
    .cpu_we_i(x_we), .cpu_adr_i(x_adr), .cpu_dat_i(x_dat), .cpu_sel_i(x_sel),
    .cpu_dat_o(x_rdat), .cpu_ack_o(x_ack), .cpu_err_o(x_err),
    .cpu_rty_o(x_rty),
    .dma_cyc_i(d_cyc), .dma_stb_i(d_stb), .dma_lock_i(d_lock),
    .dma_we_i(d_we), .dma_adr_i(d_adr), .dma_dat_i(d_dat), .dma_sel_i(d_sel),
    .dma_dat_o(d_rdat), .dma_ack_o(d_ack), .dma_err_o(d_err),
    .dma_rty_o(d_rty),
    .s_cyc_o(s_cyc), .s_stb_o(s_stb), .s_lock_o(s_lock), .s_we_o(s_we),
    .s_adr_o(s_adr), .s_dat_o(s_dat), .s_sel_o(s_sel),
    .s_dat_i(s_rdat), .s_ack_i(s_ack), .s_err_i(s_err), .s_rty_i(s_rty),
    .owner_o(owner_o));

  assign s_cyc_o = s_cyc; assign s_stb_o = s_stb; assign s_we_o = s_we;
  assign s_adr_o = s_adr; assign s_dat_o = s_dat; assign s_sel_o = s_sel;
  assign s_rdat_o = s_rdat;
  assign s_lock_o = s_lock;
  assign s_ack_o = s_ack; assign s_err_o = s_err; assign s_rty_o = s_rty;

  // ── downstream split: RAM (adr[11]=0) and DMA registers (adr[11]=1) ──
  logic          r_cyc, r_stb, r_we;
  logic [AW-1:0] r_adr;
  logic [DW-1:0] r_dat, r_rdat;
  logic [SW-1:0] r_sel;
  logic          r_ack, r_rty;

  wb_split2 #(.AW(AW), .DW(DW), .SW(SW), .SEL_BIT(11)) u_dsplit (
    .m_cyc_i(s_cyc), .m_stb_i(s_stb), .m_lock_i(s_lock), .m_we_i(s_we),
    .m_adr_i(s_adr), .m_dat_i(s_dat), .m_sel_i(s_sel),
    .m_dat_o(s_rdat), .m_ack_o(s_ack), .m_err_o(s_err), .m_rty_o(s_rty),
    .a_cyc_o(r_cyc), .a_stb_o(r_stb), .a_lock_o(), .a_we_o(r_we),
    .a_adr_o(r_adr), .a_dat_o(r_dat), .a_sel_o(r_sel),
    .a_dat_i(r_rdat), .a_ack_i(r_ack), .a_err_i(1'b0), .a_rty_i(r_rty),
    .b_cyc_o(cfg_cyc), .b_stb_o(cfg_stb), .b_lock_o(), .b_we_o(cfg_we),
    .b_adr_o(cfg_adr), .b_dat_o(cfg_dat), .b_sel_o(),
    .b_dat_i(cfg_rdat), .b_ack_i(cfg_ack), .b_err_i(cfg_err),
    .b_rty_i(1'b0),
    .hit_b_o());

  wb_shared_ram #(.AW(AW), .DW(DW), .SW(SW), .WORDS(256), .WAITS(RAM_WAITS))
    u_ram (.clk_i(clk_i), .rst_i(rst_i), .cyc_i(r_cyc), .stb_i(r_stb),
           .we_i(r_we), .adr_i(r_adr), .dat_i(r_dat), .sel_i(r_sel),
           .busy_i(ram_busy_i), .dat_o(r_rdat), .ack_o(r_ack),
           .err_o(), .rty_o(r_rty), .writes_o(ram_writes_o));
endmodule

  === SIM C - requests that do not overlap ===
    the CPU reads 0x005 and releases; then the DMA copies one word

    clk  cpu_busy dma_busy  cpu_cyc dma_cyc  owner  s_cyc s_stb   adr    term
      0     0        0         0       0      -      0     0        -
      1     0        0         0       0      -      0     0        -
      2     1        0         1       0      -      0     0        -
      3     1        0         1       0      CPU    1     1    0x005   ACK
      4     1        0         0       0      CPU    0     0        -
      5     0        0         0       0      -      0     0        -
      6     0        0         0       0      -      0     0        -
      7     0        0         0       0      -      0     0        -
      8     0        0         0       0      -      0     0        -
      9     1        0         1       0      -      0     0        -
     10     1        0         1       0      CPU    1     1    0x803   ACK
     11     1        1         0       1      CPU    0     0        -
     12     0        1         0       1      DMA    1     1    0x010   ACK
     13     0        1         0       0      DMA    0     0        -
     14     0        1         0       1      -      0     0        -
     15     0        1         0       1      DMA    1     1    0x030   ACK
     16     0        1         0       0      DMA    0     0        -
     17     0        1         0       0      -      0     0        -
     18     0        0         0       0      -      0     0        -
     19     0        0         0       0      -      0     0        -

    acquisitions  CPU 5   DMA 2      owned clocks  CPU 10   DMA 4
    clocks a master asserted CYC_O without owning: CPU 5  DMA 2
    -> one clock per acquisition, with no competitor present

  === SIM D - both masters assert CYC_O on the same clock ===
    the CPU request is timed to rise on a DMA phase boundary

    clk  cpu_busy dma_busy  cpu_cyc dma_cyc  owner  s_cyc s_stb   adr    term
      0     0        0         0       0      -      0     0        -
      1     0        0         0       0      -      0     0        -
      2     1        0         1       0      -      0     0        -
      3     1        0         1       0      CPU    1     1    0x803   ACK
      4     1        1         0       1      CPU    0     0        -
      5     0        1         0       1      DMA    1     1    0x010   ACK
      6     0        1         0       0      DMA    0     0        -
      7     1        1         1       1      -      0     0        -
      8     1        1         1       1      CPU    1     1    0x007   ACK
      9     1        1         0       1      CPU    0     0        -
     10     0        1         0       1      DMA    1     1    0x030   ACK
     11     0        1         0       0      DMA    0     0        -
     12     0        1         0       1      -      0     0        -
     13     0        1         0       1      DMA    1     1    0x011   ACK
     14     0        1         0       0      DMA    0     0        -
     15     0        1         0       1      -      0     0        -
     16     0        1         0       1      DMA    1     1    0x031   ACK
     17     0        1         0       0      DMA    0     0        -
     18     0        1         0       0      -      0     0        -
     19     0        0         0       0      -      0     0        -
     20     0        0         0       0      -      0     0        -

    acquisitions  CPU 5   DMA 4
    CPU clocks asserting CYC_O without owning  5
    DMA clocks asserting CYC_O without owning  6
    CPU clocks holding work with CYC_O negated 5
    DMA clocks holding work with CYC_O negated 5
    extra wait clocks caused by contention: CPU 0  DMA 2
    CPU read value 0xaaaa0007   DMA words 2   DMA failed 0
    violations: no-owner 0  non-owner term 0  context 0  mid-transfer 0

// ─────────────────────────────────────────────────────────────────────────
// wb_bus_probe — the instrument, not part of the design.
//
// Everything here is simulation-only observation: int counters, no reset
// requirement beyond clearing, no synthesis intent. A silicon version of
// any of it would be narrow counters behind a status register, and none of
// it is a Wishbone feature.
//
// It answers four questions that no single signal answers:
//
//   1. OWNERSHIP TIMELINE   who owns, for how long, how often it moves
//   2. REQUEST-TO-COMPLETION  how many clocks a master held work without
//      asserting CYC_O, and how many it asserted CYC_O without owning
//   3. RESPONSE ISOLATION   did a master see a termination it did not earn
//   4. REQUEST CONTEXT      does every shared field come from one master
//
// Question 2 is the one that makes the layers measurable. A master that is
// busy with CYC_O negated has a pending LOCAL request and no bus request
// at all; a master asserting CYC_O without owning has a bus request and no
// bus. Those are different clocks and they are counted separately.
// ─────────────────────────────────────────────────────────────────────────
module wb_bus_probe #(
  parameter int unsigned AW = 12,
  parameter int unsigned DW = 32,
  parameter int unsigned SW = DW/8
) (
  input  logic          clk_i,
  input  logic          rst_i,
  // client layer
  input  logic          cpu_busy_i,
  input  logic          dma_busy_i,
  // CPU master port
  input  logic          cpu_cyc_i,
  input  logic          cpu_stb_i,
  input  logic          cpu_we_i,
  input  logic [AW-1:0] cpu_adr_i,
  input  logic [DW-1:0] cpu_dat_i,
  input  logic [SW-1:0] cpu_sel_i,
  input  logic          cpu_ack_i,
  input  logic          cpu_err_i,
  input  logic          cpu_rty_i,
  // DMA master port
  input  logic          dma_cyc_i,
  input  logic          dma_stb_i,
  input  logic          dma_we_i,
  input  logic [AW-1:0] dma_adr_i,
  input  logic [DW-1:0] dma_dat_i,
  input  logic [SW-1:0] dma_sel_i,
  input  logic          dma_ack_i,
  input  logic          dma_err_i,
  input  logic          dma_rty_i,
  // shared downstream path
  input  logic          s_cyc_i,
  input  logic          s_stb_i,
  input  logic          s_we_i,
  input  logic [AW-1:0] s_adr_i,
  input  logic [DW-1:0] s_dat_i,
  input  logic [SW-1:0] s_sel_i,
  input  logic          s_ack_i,
  input  logic          s_err_i,
  input  logic          s_rty_i,
  input  logic [1:0]    owner_i,
  // violations
  output int unsigned   v_xfer_no_owner_o,
  output int unsigned   v_nonowner_term_o,
  output int unsigned   v_context_mix_o,
  output int unsigned   v_owner_change_active_o,
  // timeline
  output int unsigned   owner_changes_o,
  output int unsigned   cpu_acquires_o,
  output int unsigned   dma_acquires_o,
  output int unsigned   cpu_own_clocks_o,
  output int unsigned   dma_own_clocks_o,
  output int unsigned   none_clocks_o,
  // request-to-completion
  output int unsigned   cpu_pending_quiet_o,
  output int unsigned   cpu_req_wait_o,
  output int unsigned   dma_pending_quiet_o,
  output int unsigned   dma_req_wait_o,
  // terminations seen on the shared path
  output int unsigned   n_ack_o,
  output int unsigned   n_err_o,
  output int unsigned   n_rty_o
);
  localparam logic [1:0] OWN_NONE = 2'd0;
  localparam logic [1:0] OWN_CPU  = 2'd1;
  localparam logic [1:0] OWN_DMA  = 2'd2;

  logic [1:0] prev_owner_q;
  logic       prev_active_q;   // a phase was presented and unanswered

  logic s_term, cpu_term, dma_term, ctx_bad;
  assign s_term   = s_ack_i   || s_err_i   || s_rty_i;
  assign cpu_term = cpu_ack_i || cpu_err_i || cpu_rty_i;
  assign dma_term = dma_ack_i || dma_err_i || dma_rty_i;

  // The shared request context must be one master's, whole. RULE 3.60
  // names the fields that MUST be qualified together by [STB_O]; this
  // compares all of them against the owner's own outputs.
  always_comb begin
    ctx_bad = 1'b0;
    if (s_stb_i) begin
      if (owner_i == OWN_CPU)
        ctx_bad = (s_adr_i != cpu_adr_i) || (s_we_i != cpu_we_i)
               || (s_sel_i != cpu_sel_i)
               || (s_we_i && (s_dat_i != cpu_dat_i));
      else if (owner_i == OWN_DMA)
        ctx_bad = (s_adr_i != dma_adr_i) || (s_we_i != dma_we_i)
               || (s_sel_i != dma_sel_i)
               || (s_we_i && (s_dat_i != dma_dat_i));
    end
  end

  always_ff @(posedge clk_i) begin
    if (rst_i) begin
      v_xfer_no_owner_o <= 0; v_nonowner_term_o <= 0;
      v_context_mix_o   <= 0; v_owner_change_active_o <= 0;
      owner_changes_o   <= 0;
      cpu_acquires_o    <= 0; dma_acquires_o <= 0;
      cpu_own_clocks_o  <= 0; dma_own_clocks_o <= 0; none_clocks_o <= 0;
      cpu_pending_quiet_o <= 0; cpu_req_wait_o <= 0;
      dma_pending_quiet_o <= 0; dma_req_wait_o <= 0;
      n_ack_o <= 0; n_err_o <= 0; n_rty_o <= 0;
      prev_owner_q <= OWN_NONE; prev_active_q <= 1'b0;
    end else begin
      // 1. ownership timeline
      if      (owner_i == OWN_CPU) cpu_own_clocks_o <= cpu_own_clocks_o + 1;
      else if (owner_i == OWN_DMA) dma_own_clocks_o <= dma_own_clocks_o + 1;
      else                         none_clocks_o    <= none_clocks_o + 1;
      if (owner_i != prev_owner_q) owner_changes_o <= owner_changes_o + 1;
      // An ACQUISITION is a transition INTO an owner, which is the event a
      // reader means by "it got the bus". Returning to NONE is a release
      // and is counted separately by owner_changes_o.
      if (owner_i == OWN_CPU && prev_owner_q != OWN_CPU)
        cpu_acquires_o <= cpu_acquires_o + 1;
      if (owner_i == OWN_DMA && prev_owner_q != OWN_DMA)
        dma_acquires_o <= dma_acquires_o + 1;

      // an owner change on a clock where the previous clock had an
      // unanswered phase in flight
      if (owner_i != prev_owner_q && prev_owner_q != OWN_NONE
          && owner_i != OWN_NONE && prev_active_q)
        v_owner_change_active_o <= v_owner_change_active_o + 1;

      prev_owner_q  <= owner_i;
      prev_active_q <= s_cyc_i && s_stb_i && !s_term;

      // 2. request-to-completion
      if (cpu_busy_i && !cpu_cyc_i)
        cpu_pending_quiet_o <= cpu_pending_quiet_o + 1;
      if (cpu_cyc_i && owner_i != OWN_CPU)
        cpu_req_wait_o <= cpu_req_wait_o + 1;
      if (dma_busy_i && !dma_cyc_i)
        dma_pending_quiet_o <= dma_pending_quiet_o + 1;
      if (dma_cyc_i && owner_i != OWN_DMA)
        dma_req_wait_o <= dma_req_wait_o + 1;

      // 3. response isolation. Both masters are tested on the same clock
      // and the hits are SUMMED - two separate non-blocking assignments to
      // one counter would silently keep only the last.
      v_nonowner_term_o <= v_nonowner_term_o
        + ((cpu_term && owner_i != OWN_CPU) ? 1 : 0)
        + ((dma_term && owner_i != OWN_DMA) ? 1 : 0);

      // 4. request context + no transfer without an owner
      if (s_cyc_i && s_stb_i && owner_i == OWN_NONE)
        v_xfer_no_owner_o <= v_xfer_no_owner_o + 1;
      if (ctx_bad) v_context_mix_o <= v_context_mix_o + 1;

      if (s_ack_i) n_ack_o <= n_ack_o + 1;
      if (s_err_i) n_err_o <= n_err_o + 1;
      if (s_rty_i) n_rty_o <= n_rty_o + 1;
    end
  end
endmodule