External Pull-Ups vs Internal Weak Pull-Ups

Chapter 19.1 and 19.2 built a path from drive intent to a package pin, and neither of them can produce a HIGH. The output stage only ever pulls down; the wrapper only ever releases; the bus model asserts that a released net reads 1 and does not say why.

The why is a resistor, and on an FPGA there is a tempting shortcut: every pin has a programmable pull-up you can enable from a constraints file, at no board cost, with no component to place. This chapter is about why that shortcut does not work, stated as arithmetic rather than as a rule of thumb.

1. What Is Already Established, and What Is New Here

The general electrical argument is not this chapter's. Chapter 2.4 establishes that the restoring element is a board-level decision, one per line, and that omitting it does not give a slow bus but a bus with no HIGH at all. Chapter 11.7 derives the rise-time relationship and the Cb limits. Chapter 11.9 shows tr being spent twice — once in the clock period and once in the low phase's settling — and finds a Fast-mode-Plus deficit that is exactly tr(max).

This chapter asks one narrower question those cannot: the FPGA offers a pull-up inside the pin. Is it the right one? The answer is a number, and the number is not close.

2. The Relationship, Restated Once

A released open-drain line is an RC charge from whatever it was toward VDD:

V(t) = VDD · (1 − e^(−t / (Rp · Cb)))

I²C measures tr between 30 % and 70 % of the swing, so the specified rise time is the interval between two points on that curve:

t(30%) = Rp·Cb · ln(1/0.7)   =  0.3567 · Rp·Cb
t(70%) = Rp·Cb · ln(1/0.3)   =  1.2040 · Rp·Cb
──────────────────────────────────────────────
tr     = Rp·Cb · ln(0.7/0.3) =  0.8473 · Rp·Cb

That 0.8473 is the only constant in the chapter, and Chapter 11.7 derives it. Everything below is that one line rearranged.

3. What Each Speed Mode Allows

Rearranged for the largest resistor a mode tolerates:

Rp(max) = tr(max) / (0.8473 · Cb)

Read the table by column, not by row. Doubling the capacitance halves every allowable resistance, and capacitance is the quantity that grows when someone adds a device, lengthens a trace, or fits a connector.

There is also a floor. A pull-up strong enough to charge quickly is a pull-up whose current every device must sink while holding the line LOW:

Rp(min) = (VDD − VOL(max)) / IOL(max)

So for Fast mode at 100 pF and 3.3 V with an ordinary 3 mA sink capability, the legal window is:

967 Ω  ≤  Rp  ≤  3541 Ω

which is why 1.8 kΩ, 2.2 kΩ and 3.3 kΩ are the values that keep appearing on real boards. They are not folklore; they are the middle of that window.

4. What the Internal Pull-Up Actually Produces

Now the same equation in the other direction. Given a resistance, what rise time do you get?

tr = 0.8473 · Rp · Cb

At a modest 100 pF — a small board, a few devices, no connector:

This is not a marginal call to be resolved by measurement on a good day. It is an order-of-magnitude mismatch, and it is why the resistor is a board component.

5. Why the Failure Is Worse Than "Slow"

A too-weak pull-up does not produce a bus that runs at a lower speed. It produces a bus that is intermittently wrong at the speed you configured, which is a far harder thing to diagnose.

Chapter 11.9 shows tr being charged to the budget twice — once as part of the clock period and once inside the low phase, where the data must settle before the next rising edge. So a rise time over budget attacks two different obligations at once:

The period obligation is the forgiving one. If the line has not reached 70 % when the controller drives SCL low again, the edge is late, and a controller generating SCL from its own counter does not know or care.

The setup obligation is where data is lost. A receiver samples SDA at the SCL rising edge. If SDA is still climbing through the undefined region at that instant, the sampled value depends on where the threshold happens to sit for that device, at that temperature, at that supply voltage.

The consequence is a fault that tracks temperature, supply and which device is transmitting, and that disappears when a scope probe adds its own capacitance — or, worse, when someone slows the bus down to debug it, since halving the clock relieves the period obligation and can mask the setup one.

6. So What Is the Internal Pull-Up For?

It is a real feature with real uses, none of which is a bus.

Keeping an unused input from floating. A CMOS input left floating draws current and picks up noise. A weak pull-up answers that completely, and nothing about it needs to be fast.

Defaulting a configuration or strap pin. Read once at power-on, microseconds available, no edge rate requirement.

Holding a reset or interrupt line idle where the timing requirement is "eventually".

What those share is that nothing measures the rising edge. The moment an edge rate enters a timing budget — which for I²C is immediately, and twice — a weak pull-up is the wrong component.

7. Working a Real Choice

The method, in the order the quantities become known:

1. Count the capacitance, do not assume it. Sum every device's pin capacitance from its datasheet, add the trace, add every connector. If a daughter board can be attached, add its contribution too — and note that Cb then becomes a function of what is plugged in.

2. Take tr(max) from the speed you actually need, not the fastest the parts support.

3. Compute the ceiling. Rp(max) = tr(max) / (0.8473 · Cb).

4. Compute the floor from the weakest sink on the bus: Rp(min) = (VDD − VOL(max)) / IOL(max). The weakest device sets this, not the FPGA.

5. Check the window is not empty. If Rp(min) > Rp(max) there is no legal resistor, and the fix is architectural — fewer devices, a shorter bus, a slower mode, a bus buffer, or splitting the segment. Chapter 11.9 reaches exactly this outcome and calls it result 3.

6. Choose inside the window with margin at both ends, then measure the edge on hardware. The arithmetic assumes a single lumped RC; a real board is neither single nor lumped.

7. Leave the FPGA's internal pull-up disabled unless you are deliberately using it for step 4 of bring-up.

8. ASIC Contrast, Briefly

The arithmetic is identical; the authority differs. An ASIC I/O ring can include a genuine open-drain cell with a specified IOL at a specified VOL, so step 4's floor is a number you own rather than one you look up per family. Some ASIC pad libraries also offer a controlled on-chip pull-up characterised well enough to appear in a budget — which is a different proposition from an FPGA's weak pull-up, and the difference is characterisation, not topology.

What does not change is that Cb lives on the board. No amount of on-chip capability makes the bus capacitance smaller.

9. Misconceptions

10. Debugging

# The FPGA constraints for an I2C bus, on a board whose pull-up footprints were
# left unpopulated because "the FPGA can do it":
#
#   set_property PULLUP true   [get_ports sda_pin]
#   set_property PULLUP true   [get_ports scl_pin]
#
# (Property names are vendor-specific; the shape is what matters.) The bus was
# configured for Fast mode, 400 kHz, because the sensor supports it.
#
# The reasoning was: the pins need to idle high, the FPGA can make them idle high,
# so the resistors are redundant and the BOM gets two fewer parts.
#
# What the reasoning leaves out is that the specification does not constrain the
# idle LEVEL. It constrains the RISE TIME -- and it does so twice, once in the
# clock period and once in the low phase where data must settle before the next
# rising edge (Chapter 11.9).
#
# Effective internal pull-up for this family and I/O bank: roughly 20 kilohm.
# Measured bus capacitance, FPGA board alone:            about  55 pF
# Measured bus capacitance, with the sensor module:      about 140 pF

11. Reason It Through

12. Questions

13. What This Chapter Settled

tr = 0.8473 · Rp · Cb, and both ends of Rp are constrained: the ceiling by the rise time the mode allows, the floor by the current the weakest device can sink. For Fast mode at 100 pF and 3.3 V that window is roughly 970 Ω to 3.5 kΩ, which is where the familiar 1.8 kΩ, 2.2 kΩ and 3.3 kΩ values come from.

An FPGA's internal weak pull-up is an order of magnitude outside that window. It is a genuine feature for holding unused inputs and strap pins, where nothing measures the edge — and on an I²C bus, two things measure the edge, twice each.

With the pull-up justified, the bus now has a real HIGH and a real rising edge, and that edge takes time. The next problem follows directly: those two lines are asynchronous to the FPGA's clock, and the edge that takes 250 ns to arrive may be sampled by a flip-flop at any point during it. Chapter 19.4 owns the argument Module 18 deliberately deferred — what a synchronizer protects, and what simulation can and cannot prove about it.