Reasoning About Open-Drain, Pull-Ups and Rise Time

This is the question every I²C interview and every board review eventually reaches, and the reason it is worth working end to end is that each answer forces the next one. Nothing in the chain is a convention.

Chapter 11.7 derives the two bounds on the pull-up and 2.4 introduces them. This chapter does not re-derive them. It takes the part that decides whether a real board works: the capacitance in those equations is an estimate, and the resistor is a decision made against it.

1. The Chain, and What Breaks at Each Link

Work it forward. Each step is forced by the one above, and the right-hand column is the test of that — what would have to be true for the step to be avoidable.

The third row is where the argument is actually made, and it is worth being precise about the alternative, because "we could just guarantee one driver" sounds reasonable. It fails on acknowledge. The acknowledge bit is a slot in which the transmitter releases and the receiver pulls, and there is no instant at which the protocol can guarantee only one of them is driving — the handover is the point. Arbitration is worse: it is defined as two controllers driving simultaneously and the wire resolving. Both features exist because the electrical layer makes simultaneous driving safe, and they would have to be removed along with open-drain.

2. Two Bounds From Opposite Directions

Stated, not derived — 11.7 does that.

Rp(min) = (Vdd − VOL) / IOL              a DC limit
Rp(max) = tr(max) / (0.8473 × Cb)        an AC limit

They are not the same kind of claim, and the difference is the whole content of this chapter.

Rp(min) is about current, and it does not contain Cb. The device pulling the line low is specified to sink IOL and still hold below VOL. A smaller resistor asks it to sink more than it promised, and the "low" rises until some receiver on the bus stops seeing a low. This bound depends only on the supply and the device — both of which are known exactly at schematic time.

Rp(max) is about time, and it is inversely proportional to Cb. The line rises as an RC and the mode bounds how long that may take. Cb is the one quantity in either equation that nobody knows.

3. What Fails at Each Extreme, and How You Would Know

The two failures look nothing alike, which is useful: the symptom identifies the end.

Too small (below Rp(min)). A device pulling low cannot get the line far enough down. The bus does not stop working — it works, with a VOL that has risen toward some receiver's VIL(max). The signature is a failure that tracks which devices are on the bus and how many, that gets worse when several are pulled simultaneously, and that responds to temperature because an output transistor's on-resistance does. Edges look fast and clean on a scope; what is wrong is the level, not the shape. Steady-state current is also higher — Vdd/Rp per line whenever anything is pulling — which matters on a battery.

Too large (above Rp(max)). The line still reaches a valid high; it reaches it late. The signature is a failure that tracks speed mode and appears nowhere at 100 kHz, because Standard-mode allows 1000 ns of rise and Fast-mode allows 300 ns for the same physical edge. It also tracks position on the bus, because the device furthest from the pull-up sees the most degraded edge.

That caption is the sentence worth keeping. Moving from Standard-mode to Fast-mode does not make the edge slower; it shortens tHIGH(min) from 4.0 µs to 0.6 µs and tr(max) from 1000 ns to 300 ns, while the physics on the board stays exactly as it was. This is why "it works at 100 kHz so the hardware is fine" is close to the opposite of the truth (24.4 §6).

4. The Quantity Nobody Knows

Cb is not measured before a board is built. It is a sum of estimates:

  controller pad     10 pF     from the datasheet -- reliable
  3 sensor pads      24 pF     3 x 8 pF, from datasheets -- reliable
  trace              40 pF     length x a per-unit figure -- an estimate
  connector          15 pF     a guess informed by the part -- an estimate
  ------------------------------
  total              89 pF

The first two rows are datasheet numbers. The last two are the ones that move, and they move in one direction: late additions — a mezzanine, a longer harness, a repositioned connector, a second board on the same bus — only ever add. Nothing removes capacitance from a design after the schematic is frozen.

Combine that with §2's asymmetry and the situation is sharper than "there is a window". Rp(min) does not move with Cb, so a fitted resistor can only ever leave the window from one side: Cb grows, Rp(max) falls, and one day it falls below the value already soldered on a thousand boards.

So the margin figure worth quoting in a review is not a percentage of the window. It is a single number: the capacitance at which the fitted resistor stops meeting tr(max).

   K = math.log(0.7 / 0.3)

   # ... MODES: tr(max) and Cb(max) per speed mode, from UM10204 Table 10 ...

   def rp_min(vdd, iol, vol=0.4):  return (vdd - vol) / iol
   def rp_max(tr, cb):             return tr / (K * cb)
   def cb_at(tr, rp):              return tr / (K * rp)          # the inverse

   cb_break = cb_at(tr, rp_fitted)
   headroom = cb_break / cb_est
   # ... the window and the rise time at the estimate are reported first ...
   print(f"  Cb at which this resistor stops meeting tr(max) : {cb_break*1e12:.0f} pF")
   print(f"  headroom on the capacitance ESTIMATE            : x{headroom:.2f}"
         f"  ({(headroom-1)*100:+.0f} %)")

5. Three Boards, Audited

Board A -- 3.3 V Fast-mode, 4.7 k fitted by habit
  FITTED VALUE IS OUTSIDE THE WINDOW (above Rp(max)): [967, 3978] R

Board A -- the same board with 2.2 k
  window [967, 3978] R -- the fitted value is inside it
  rise time at the estimate : 166 ns  (limit 300 ns)
  Cb at which this resistor stops meeting tr(max) : 161 pF
  headroom on the capacitance ESTIMATE            : x1.81  (+81 %)

Board A -- the same board with 1.0 k
  window [967, 3978] R -- the fitted value is inside it
  rise time at the estimate : 75 ns  (limit 300 ns)
  Cb at which this resistor stops meeting tr(max) : 354 pF
  headroom on the capacitance ESTIMATE            : x3.98  (+298 %)

Three readings, and the first is the one that catches people.

4.7 kΩ is not legal for Fast-mode on this board. It is the value everybody fits, and at 89 pF — an optimistic capacitance for a real board — Rp(max) is 3978 Ω. Fitting it does not produce an obvious failure; it produces a rise time of 355 ns against a 300 ns limit, which works at room temperature on the near device and is the exact configuration 24.3's first bring-up case failed with.

2.2 kΩ is legal and has 81 % headroom. That sounds comfortable and is not: +81 % means the design tolerates Cb growing from 89 pF to 161 pF, and a mezzanine board plus a 30 cm harness adds more than 72 pF on its own.

1.0 kΩ costs almost nothing and buys 4×. It is barely above the 967 Ω DC floor, so it is using the window rather than sitting in the middle of it, and the price is 3.3 mA per line while anything is pulling — real on a coin cell, negligible on a powered board.

That last comparison is the design rule this chapter produces, and it is not the intuitive one:

Fit toward the bottom of the window, not the middle. The floor is fixed by quantities known exactly; the ceiling moves with a quantity that is estimated and only ever grows. Centring the value splits margin evenly between a bound that cannot move and a bound that can.

Now a board where the estimate was not optimistic:

  Cb budget: controller_pad 10 pF, eeprom 8 pF, trace 70 pF, mezzanine 120 pF,
             cable 180 pF  ->  388 pF

Board B -- 3.3 V Fast-mode
  WINDOW EMPTY at the estimate: Rp must be >= 967 R and <= 913 R.
  No resistor works. The levers are supply, sink current, capacitance,
  speed mode, or a non-resistive pull-up -- not a different resistor.

Board B -- dropped to Standard-mode instead
  window [967, 3042] R -- the fitted value is inside it
  rise time at the estimate : 723 ns  (limit 1000 ns)
  Cb at which this resistor stops meeting tr(max) : 536 pF
  headroom on the capacitance ESTIMATE            : x1.38  (+38 %)
  note: that is above the Standard-mode Cb ceiling of 400 pF,
        so the specification's own limit binds before this resistor does.

6. When the Window Is Empty

An empty window is a categorical result, not a tight one: no resistor value satisfies both bounds, so no amount of trying different resistors helps. This is the situation that produces weeks of substituting parts.

The levers, in the order a real project can usually apply them:

The third and fifth rows are the same observation from two directions, and they are why Fast-mode Plus exists as a speed grade rather than as Fast-mode with a faster clock. 11.7 works that case in detail.

The Board B result shows the first lever applied, and it also shows why the answer is not simply "use Standard-mode and relax". At 388 pF with 2.2 kΩ, the headroom is +38 % and the specification's own 400 pF ceiling binds before the resistor does — so the board is close to being out of specification for reasons that have nothing to do with the resistor, and the real finding is that the bus grew past what a single segment should carry. A buffer splitting it into two segments addresses the cause; a different resistor addresses the symptom until the next cable.

7. What the Arithmetic Cannot Tell You

All of §5 is calculation on estimates, and it is worth being exact about what that does and does not buy.

It cannot tell you Cb. That is the input. Every number downstream inherits the estimate's error, and the numbers do not become measurements by being printed to three digits.

It assumes a single lumped capacitance. A real bus is distributed, and a long trace with a stub behaves differently from the same capacitance concentrated at the pull-up — which is how a bus can meet the calculation and still show ringing that a filter then has to deal with.

It says nothing about noise, coupling, or ground. A rise time within limits can still be unusable if the edge is riding on switching noise from a nearby regulator.

The first genuinely honest measurement of Cb is the rise time on a scope, at step 2 of 24.3's bring-up order — and that is worth stating as a positive, not a caveat. One measurement inverts the equation: Cb = tr / (0.8473 × Rp). A measured rise time that disagrees with the estimate is itself the finding, because it means Cb is not what was assumed and every other quantity derived from Cb is wrong by the same factor.

8. Common Misconceptions

"4.7 kΩ is the standard I²C pull-up." It is the most common value and it is outside the window for Fast-mode on a board with 89 pF of capacitance. There is no standard value; there is a window that depends on the supply, the sink current, the speed mode and the capacitance.

"A bigger resistor is safer because it draws less current." It draws less current and it slows the edge, and the edge is what the timing budget is spent on. Below Rp(min) the failure is a level; above Rp(max) it is a time. Both are failures.

"The window's midpoint is the safest choice." The midpoint splits margin evenly between a bound that cannot move and one that only ever moves toward you. §5 measures the difference: 2.2 kΩ tolerates Cb growing 1.8×, 1.0 kΩ tolerates 4×, and both are legal.

"We measured the rise time and it is fine, so the pull-up is right." It shows the AC bound is met on that board at that temperature. It says nothing about the DC bound, which is about whether a device pulling low can still reach VOL — a different measurement, on the low level rather than the edge.

"Internal pull-ups will do." They are typically tens of kilohms and specified loosely. 19.3 works the arithmetic: at 20 kΩ into 55 pF the rise is already 932 ns, which fails Fast-mode outright and is marginal for Standard-mode before any board capacitance is added.

// A Fast-mode bus, 2.2k pull-ups, working for a year across a production run.
// A mezzanine board is added to the product to carry two extra sensors.
//
// Cb budget, as it was at design time:
//    controller pad   10 pF
//    eeprom            8 pF
//    trace            70 pF
//                     ------
//                     88 pF   ->  Rp(max) = 4022 ohm.  2.2k is comfortable.
//
// Nobody recomputed it when the mezzanine and its ribbon were added:
//    + mezzanine     120 pF
//    + cable         180 pF
//                     ------
//                    388 pF   ->  Rp(max) =  913 ohm.  2.2k is now ILLEGAL.
//
// And Rp(min) at 3.3 V with 3 mA devices is 967 ohm. 967 > 913: the window
// is EMPTY. No resistor value works at Fast-mode on this bus any more.

Fit a bus buffer and split the bus into two segments, each with its own
pull-ups: the on-board segment keeps its 88 pF and its 2.2k, and the mezzanine
segment gets its own pull-up sized for its own capacitance. That addresses the
cause -- one segment had grown past what a single segment can carry.

If a buffer is not available, the ranked alternatives and their costs:
 drop to Standard-mode      window reopens to [967, 3042]; costs throughput
 stronger-sink devices      lowers the floor; a BOM change
 shorten the ribbon         lowers Cb; may not be possible mechanically

And add the recomputation to the change process. The design-time number was
correct; what failed was that a mechanical change altered an electrical input
and nothing recomputed the electrical output.

// Reported symptom: occasional data corruption at 400 kHz. Engineer reasons
// correctly that a slow edge is a common cause, and fits 470 ohm to be sure.
//
// The corruption gets worse, and now a second device fails too.
//
//    Vdd  = 3.3 V
//    the devices on this bus are specified IOL = 3 mA at VOL = 0.4 V
//
//    Rp(min) = (3.3 - 0.4) / 3 mA = 967 ohm
//
// 470 ohm is HALF the minimum. A device pulling low now has to sink 7 mA to
// hold 0.4 V -- more than twice what it guarantees -- so it does not, and the
// "low" sits at whatever voltage its output transistor reaches at 3 mA.

Compute both bounds before changing the value:

  Rp(min) = (Vdd - VOL) / IOL      = 967 ohm   <- a floor, not a suggestion
  Rp(max) = tr(max) / (0.8473 Cb)

then fit just above the floor -- 1.0k here, which Section 5 shows buys 4x
headroom on the capacitance estimate while staying legal.

If 1.0k still does not meet tr(max), the window is empty and the resistor is
the wrong lever entirely: Section 6's table is the list of levers that remain,
and every one of them is a change to something other than the resistor.

9. Reason It Through

A. A board runs at 3.3 V, Fast-mode, with Cb estimated at 150 pF, and the devices are ordinary 3 mA parts. Someone proposes 3.3 kΩ. Work the decision and state what you would still want to know.

The floor is (3.3 − 0.4)/3 mA = 967 Ω. The ceiling is 300 ns / (0.8473 × 150 pF) ≈ 2360 Ω. So 3.3 kΩ is above the ceiling and not legal — rise time would be about 419 ns against a 300 ns limit. Something between 1.0 kΩ and 2.3 kΩ is legal, and by §5's rule the lower end is better: 1.0 kΩ breaks at 300 ns / (0.8473 × 1000) ≈ 354 pF, so it tolerates Cb growing 2.4× from the estimate. What I would still want to know is where the 150 pF came from — specifically whether it includes the connector and anything that attaches through it — because that is the term that moves, and the whole margin calculation is downstream of it.

B. Why can a bus fail its DC bound while every edge on a scope looks perfect?

Because the two bounds constrain different quantities. Rp(max) constrains the shape of the rising edge; Rp(min) constrains the voltage the line reaches when a device is pulling it down. A resistor below the floor draws more current than the device guaranteed to sink, so the low level rises — and a rising low level does nothing to the edge, which is still an RC into the same capacitance with a smaller resistor, and therefore faster and cleaner than before. Looking at edges is looking at the wrong measurement entirely; the one that matters here is a DC level on the low phase, and it has to be read against each receiver's VIL(max), which is not the same number for every device on the bus.

C. Two engineers disagree. One says fit the middle of the window for maximum margin; the other says fit near the bottom. Settle it.

The second is right, and the reason is asymmetry rather than preference. Rp(min) is computed from the supply, the specified VOL and the specified IOL — all known exactly at schematic time, none of which change after the board is built. Rp(max) is computed from Cb, which is estimated and which only ever grows, because nothing removes capacitance from a product after the schematic freezes. So margin toward the floor protects against nothing, and margin toward the ceiling protects against the one thing that actually happens. §5 puts numbers on it: on the same board, 2.2 kΩ tolerates a 1.8× capacitance growth and 1.0 kΩ tolerates 4×, both legal, and the price of the second is a few milliamps. The middle is only correct if both bounds are equally uncertain, and they are not.

D. A product must support both Standard-mode and Fast-mode Plus on the same bus, selectable in software. What does that requirement do to the pull-up decision?

It removes the resistor's freedom almost entirely, because the bus must satisfy the tightest constraint of any supported mode at all times — the pull-up is a physical part and does not change when software changes speed. Fm+ demands tr ≤ 120 ns, so at any realistic Cb the ceiling collapses: at 150 pF it is 120 ns / (0.8473 × 150 pF) ≈ 944 Ω, which is below the 967 Ω floor for 3 mA devices at 3.3 V. The window is empty, and the requirement has quietly become a device-selection requirement: every part on the bus needs an Fm+-class sink, which is the 20 mA specification, and that drops the floor to 145 Ω and reopens the window. The right output of this analysis is not a resistor value but a line in the BOM constraints — and a note that "software-selectable speed" is a hardware decision made at schematic time.

10. Understanding Check

11. What 24.5 Settled

Open-drain is forced, not chosen. A shared wire, plus acknowledge and arbitration as features, plus no short-circuit, leaves exactly one electrical arrangement — and the pull-up follows from it, because after open-drain nothing can source a high.

The two bounds are different kinds of claim. The floor is DC, computed from exactly-known quantities, and contains no capacitance term. The ceiling is AC and is inversely proportional to the one quantity nobody knows.

Therefore fit toward the bottom of the window. Measured on one board: 2.2 kΩ tolerates Cb growing 1.8×, 1.0 kΩ tolerates 4×, both legal, and the difference in cost is a few milliamps. Centring the value spends margin on a bound that cannot move.

The margin figure to quote is a capacitance, not a percentage. Cb_break = tr(max)/(0.8473 × Rp) is directly comparable against the next mechanical change, which is what actually consumes the margin.

The two failure ends have opposite signatures. Too large: edge shape, speed-dependent, worse far from the pull-up. Too small: edge shape fine, low level wrong, depends on which device is pulling, worse with temperature. Knowing which you are looking at is most of the diagnosis.

And one measurement checks all of it. A scope on a rising edge inverts to a measured Cb, and every capacitance-derived number on the board is corrected by the same ratio.

The next chapter takes the second mechanism that rests on the wired-AND — a target holding SCL low — and works the same way, from the device's reason through the bus mechanism to the obligation it creates on somebody else's design. Chapter 24.6 — Reasoning About Clock Stretching.