Wiring a Real I²C Bus — Devices, Pull-Ups, Supplies and Segments

Chapter 3.2 established a topology in the abstract: two rails, several targets, identity carried in the transmitted information. Every claim in it was true and every claim in it quietly assumed the wiring works.

This chapter is the design review. It takes one concrete board, walks it device by device, and asks the questions a reviewer actually asks — where do the resistors go, what does each part\u0027s supply rail decide, what happens to the bus when the sixth device is fitted, and when does one bus stop being one bus. Module 2 supplied the physics; this is the board-level consequence of it.

1. The Board

One board, used throughout the chapter so the reasoning accumulates rather than resetting.

2. Pull-Ups Belong to the Bus, Not to the Devices

Chapter 2.4 derived how to size a pull-up — the ceiling from rise time against the loading, the floor from what the weakest device can sink, and the window between them. None of that is repeated here. What this chapter owns is a different and more frequently botched question: how many pull-ups should the board have, and where?

The answer is simpler than the mistake it prevents. A segment needs one effective pull-up per line. Not one per device. The resistor serves the conductor, and there is one conductor.

That sounds obvious stated baldly, and it is violated constantly, for a structural reason: modules are designed to work standalone. A sensor breakout, a daughter board, a plug-in module — each is sold to be usable on its own, so each carries its own pull-ups. Populate two such modules on one bus and the board now has two pull-up pairs in parallel, neither of which anybody chose.

The arithmetic

Resistors in parallel combine as:

   1 / Req  =  1/R1  +  1/R2  +  ...  +  1/Rn

For two equal resistors that reduces to Req = R / 2. Work the common case: the host board fits a 4.7 kilohm pull-up, and a plug-in module brings its own 4.7 kilohm pull-up.

   1 / Req  =  1/4700  +  1/4700
            =  2/4700
       Req  =  2350 ohm

The bus now has a 2.35 kilohm effective pull-up where the design intended 4.7 kilohm. Three consequences, and the third is the one that bites:

Rising edges get faster. More charging current for the same capacitance. On its own this is harmless and occasionally welcome.

LOW-state current roughly doubles. Every device that pulls the line LOW now sinks about twice the current it would have. By Chapter 2.4\u0027s floor, that is the constraint that can be violated: a device specified to hold a valid LOW while sinking a certain current may no longer be able to, and the symptom is an elevated LOW level that receivers misread — which looks like data corruption rather than an electrical limit.

Nobody made the decision. The effective value is an accident of which modules were populated. Fit a third module and it becomes roughly 1.57 kilohm; the design has drifted with the bill of materials.

3. What a Device\u0027s Supply Rail Decides

Every device on the bus has a supply, and the bus has a pull-up rail. Those are separate facts, and their relationship decides whether the arrangement works.

Chapter 2.6 developed the electrical detail; the board-level statement is this: the released bus sits at the pull-up\u0027s rail, and every attached device must be able to live with that voltage. Two independent requirements follow, and a device can satisfy one and fail the other:

It must read the level as HIGH. A device\u0027s input threshold is generally referenced to its own supply, so a part running from a higher rail than the pull-up may never see a valid HIGH. Nothing is damaged; the bus simply does not work, and it may work at room temperature and stop elsewhere.

It must tolerate the level. A part running from a lower rail than the pull-up has its input sitting above its own supply whenever the bus is released. Whether that is acceptable is a property of that specific pin — some are specified to tolerate it and many are not — and the datasheet is the only authority.

There is a third, easily forgotten case: what happens when one domain is powered down while the bus stays active. Pin protection structures conduct toward a supply that is not there, so a released bus can push current into an unpowered part. On a board where a subsystem can be switched off independently, that is a bus question, not only a power question.

When domains genuinely must be mixed, the answer is a bidirectional level translator with each segment carrying its own pull-up to its own rail, which Chapter 2.6 covers. What matters architecturally is that translation splits the bus into segments — which is the subject of the rest of this chapter.

4. Loading Accumulates — and the Connector Is the Cliff

Chapter 2.4\u0027s Example D showed a design window closing when capacitance grew. This is where that capacitance comes from on a real board.

Each device contributes its pin and input structure. Each centimetre of routed copper contributes. Every test point, protection device and translator contributes whether or not it is doing anything. These add up quietly, and a bus that works with four devices can misbehave with seven without any component having changed.

The connector in Figure 1 deserves separate attention, because it is qualitatively different from the rest. Everything else on the board is known at design time and can be budgeted. A connector is a point at which the board loses control of what is attached: a cable of unknown length, a daughter board with unknown device count, and — as §2 established — possibly its own pull-ups. It is simultaneously the largest single capacitance contributor and the least predictable one.

Three review habits follow:

Budget the worst case, not the bench case. Characterise the bus with the maximum configuration the product permits, including the longest sanctioned cable. A bus measured with two devices on a bench and shipped into a seven-device system was not measured.

Treat anything past a connector as a separate design problem. Its loading is somebody else\u0027s decision.

Keep the bus physically compact where you can. Long routes and stubs buy nothing and cost capacitance. This is one of the few places where routing discipline directly converts into protocol margin.

5. When One Bus Stops Being One Bus

Sometimes the right answer is not a better resistor but a second bus. Six distinct reasons, and they are worth recognising separately because they have different remedies:

Too much capacitance. The design window from Chapter 2.4 has closed — no resistor satisfies both the rise-time ceiling and the sink-current floor. Splitting the load gives each segment its own window.

Duplicate identities. Two parts that answer to the same identity cannot share a segment, for the reason Chapter 3.2 diagnosed. If neither can be re-strapped, they must not see the same transfers.

Different voltage domains. §3\u0027s problem. Translation inherently produces two segments.

Fault isolation. One device holding a line LOW takes down every participant that shares that conductor. If part of the system must keep working when another part fails, they cannot be on the same segment.

Physical distance or topology. A subsystem across a cable or on a separate board is a segment whether or not anybody planned it that way.

Independent power. A subsystem that can be switched off while the rest runs raises §3\u0027s powered-down question. Isolating it keeps an unpowered domain from loading a live bus.

Four kinds of component do this job, and the differences matter more than the names:

A multiplexer or switch connects the host\u0027s segment to one of several downstream segments at a time. This is the tool that solves duplicate identities: two parts with the same identity live on different downstream branches, and the host reaches them by selecting a branch first. Notice what that implies — the host must now configure the mux before addressing the target, so a device\u0027s logical address is no longer sufficient to reach it. That is a real change to the software model.

A buffer or repeater does not select; it isolates capacitance so each side presents its own load to its own pull-up, letting a longer or more heavily loaded bus work. It must be bidirectional and must preserve dominant LOW, for the reasons Chapter 2.6 gave about translators.

A level translator is a repeater that also crosses a voltage domain.

A bridge converts to a different bus entirely, and is out of scope here.

These are described conceptually on purpose. Real parts differ in whether they pass a held line, how they behave at power-up, whether they add delay that eats timing margin, and what happens when a downstream segment is stuck — all of which are device-specific and belong to the datasheet rather than to a curriculum. What this chapter establishes is why you would reach for one, and the constraint every candidate must satisfy: bidirectional, and dominant-LOW preserving.

6. RTL Policy for This Chapter

There is no executable RTL here, and that is a deliberate judgement rather than an omission.

This chapter\u0027s subject is resistors, copper, supply rails, connectors, accumulated capacitance and physical topology. None of it is behaviour that a simulator can evaluate: synthesis creates no resistor, no trace and no connector, and an HDL model of a voltage domain would be a fiction that teaches the wrong thing. The parallel-resistance arithmetic in §2 is the chapter\u0027s real quantitative content, and it is arithmetic rather than logic.

A segment-selection model was considered and rejected for a second reason: it would duplicate Chapter 3.2\u0027s target_decoder almost exactly — one selector input, one-hot enables out — while teaching nothing new, and this module deliberately avoids two models of the same shape. Where executable hardware genuinely belongs in Module 3 is on either side of this chapter: the role structure in 3.1, the selection abstraction in 3.2, and the register shell in 3.4.

7. Debugging — The Bus That Broke When the Second Module Was Fitted

// A host board carries one I2C bus with a 4.7 kilohm pull-up pair, sized against
// its own loading, and it works. The product supports two plug-in sensor modules
// on a connector. Each module was designed to be usable standalone on an
// evaluation setup, so each carries its own 4.7 kilohm pull-up pair -- populated,
// because that is what made it work on the bench.
//
// The integration reasoning is:
//
//   "Pull-ups only pull the line up. More of them can only make the HIGH
//    stronger, and a stronger HIGH is not a hazard."
//
// The first half is true. The conclusion does not follow.
//
// Fitted configurations shipped to test:
//   host only                      -> 4.7k                 (as designed)
//   host + one module              -> 4.7k || 4.7k = 2.35k
//   host + both modules            -> 4.7k || 4.7k || 4.7k = 1.57k

// One effective pull-up pair per segment, and it is a decision somebody makes.
//
//   1. Depopulate the module pull-ups when the module joins a bus that already has
//      them. Modules intended for both standalone and integrated use should fit
//      these as OPTIONAL footprints, documented as such.
//   2. Re-size the remaining pair against the full loading, using Chapter 2.4's
//      window: the ceiling from rise time with all modules fitted, the floor from
//      the WEAKEST device's sink capability -- here the PMIC, not the sensors.
//   3. If the window is empty with everything fitted, the bus needs a repeater or
//      a second segment rather than a compromise resistor (section 5).
//
// The review question that prevents it entirely: for this bus, in every shippable
// configuration, WHICH pull-up pair is populated and what loading was it sized
// against? If nobody can answer for all configurations, the effective resistance
// is an accident of assembly.
//
// The measurement that catches it: check the LOW level with the MAXIMUM
// configuration fitted and at temperature, on the weakest device's pin. Rising
// edges will look better than ever; the LOW level is where the fault shows.

The engineering lesson: on a shared bus, an electrical parameter can be set by the bill of materials rather than by a designer. Pull-ups are the common case because every module wants to work standalone, but the general shape recurs — anything a module contributes to a shared conductor combines with what every other module contributed. When a bus fails on a particular combination of populated boards, look for a parameter that combines rather than for a device that broke. And when one symptom improves while another degrades, distrust the one that improved: faster edges and an elevated LOW are the same cause seen from two sides.

8. Common Misconceptions

9. Reason It Through

Work these through before reading the answers.

A host board fits 4.7 kilohm pull-ups. A daughter board with its own 4.7 kilohm pull-ups is fitted. What is the effective resistance, and which device is most likely to fail first?

Answer. 1/Req = 1/4700 + 1/4700, so Req = 2.35 kilohm — half the intended value, and every device now sinks roughly twice the budgeted current while holding a line LOW. The device most likely to fail is the one with the weakest sink capability, which is often not one of the newly fitted parts. That is what makes the fault confusing: the symptom appears on a device nobody changed.

A 1.8 V sensor must join a bus whose pull-ups go to 3.3 V. List what has to be checked before assuming this works.

Reasoning. Two independent questions, plus one that is easy to forget. Can the sensor\u0027s pin tolerate 3.3 V when the bus is released — a datasheet property, not an assumption? Will the sensor recognise the released level as HIGH against its own threshold — usually yes when the pull-up rail is higher, which is why this direction fails less often than the reverse? And what happens if the 1.8 V domain is powered down while the bus stays active? If any answer is unsatisfactory, the arrangement needs a bidirectional translator, which splits the bus into two segments each with its own pull-up.

Two identical sensors must both be read, and neither has a configurable identity. Give two architectural options and say what each costs.

Reasoning. Put them on separate segments behind a mux, which costs a component, board area, and a change to the software model — the host must select the branch before addressing the sensor. Or choose a different part for one position that offers a configurable or different fixed identity, which costs a second part number and qualification. What does not work is any firmware approach: both devices answer every matching transfer, and by Chapter 3.2\u0027s reasoning the controller receives the wired-AND of their responses before software is involved.

A bus works with four devices. Six more are added behind a connector and it fails. Describe the diagnostic order.

Reasoning. Electrical before protocol, and shape before level. Look at an edge: if rising edges have slowed while LOW stays clean, the added devices and cable increased capacitance and the pull-up can no longer charge it in time — recompute Chapter 2.4\u0027s window against the new loading. If instead the LOW level has risen, suspect pull-ups arriving with the new hardware. If the window is empty either way, the remedy is a repeater or a second segment, not a resistor value. Only after the electrical layer is sound is it worth reading the protocol.

10. Understanding Check

11. Summary

The abstract topology becomes a schematic, and the schematic has constraints the abstraction hid.

Pull-ups belong to the bus. One effective pair per segment, sized deliberately. The common failure is modules each bringing their own — two 4.7 kilohm pairs in parallel give 2.35 kilohm, which speeds up rising edges and roughly doubles the current every device must sink while holding a line LOW. The visible symptom improves while the dangerous one degrades.

A device\u0027s supply rail decides two independent things: whether it can tolerate the released level, and whether it recognises that level as HIGH. Neither implies the other, and a domain that can be powered down separately raises a third question, because protection structures load a live bus regardless.

Loading accumulates from pins, copper, test points and translators — and a connector is the cliff, because past it the board no longer controls what is attached. Budget the worst shippable configuration, not the bench.

One bus stops being one bus for six distinct reasons: capacitance, duplicate identities, voltage domains, fault isolation, distance, and independent power. Muxes and switches select a branch and therefore change the software model; buffers and repeaters isolate loading without selecting; translators cross a domain. Every candidate must be bidirectional and must preserve dominant LOW, or it breaks the mechanisms Module 2 established.

No executable RTL appears here, because resistors, copper and supply rails are not behaviour — and a segment-selection model would only duplicate Chapter 3.2\u0027s decoder.

12. What Comes Next

The bus is now a real, buildable, reviewable piece of hardware. What remains is the other side of the host pin: Chapter 3.4 goes inside the SoC and follows a transfer from software down to the conductor — the register interface a driver actually writes, the controller peripheral that turns a register write into bus activity, how completion and failure come back as status and interrupts, and where the open-drain boundary from Module 2 sits in that stack.

Browse the full path on the I\u00B2C tutorials index. For the sizing window this chapter relies on, see Pull-Up Resistors; for thresholds and translation, Real Bus Electrical Behavior.