Pull-Up Resistors — Sizing, Rise Time and Bus Capacitance

Chapter 2.3 ended on a question it had made unavoidable. Every device can pull the conductor LOW or release it, and none can drive it HIGH — so a released conductor is attached to nothing, and a conductor attached to nothing has no defined level. Something outside the devices has to restore it.

The answer is a resistor to the positive supply, one per line, fitted on the board. That sounds like a footnote and is not: the way it restores HIGH determines the shape of every rising edge on the bus, which makes it a timing component as much as an electrical one. This chapter derives that consequence and then shows why "which resistor" is a question with a range for an answer.

1. The Restoring Element

Connect a resistor between the conductor and the positive supply. Leave everything else as Chapter 2.3 left it.

Two cases now have defined outcomes.

No device is pulling. Every switch is open, so nothing connects the conductor to ground. The resistor provides the only path to anywhere, and it goes to the supply — so the conductor is pulled toward the supply and settles HIGH.

At least one device is pulling. That device's switch connects the conductor to ground through a low-impedance path. The resistor is still connected to the supply, so current flows through it, through the conductor, and into the pulling device — but the resistor is deliberately a much weaker path than the switch, so the conductor sits close to ground. The bus is LOW.

The asymmetry in that figure is the entire subject of the chapter. One weak path upward, permanently connected. Several strong paths downward, switched. LOW is actively driven; HIGH is passively recovered. Everything that follows is a consequence of those two sentences not being symmetric.

2. HIGH Is Not Instant

Here is where the resistor stops being a detail.

When a device pulls the conductor LOW, it does so through a low-impedance switch. Charge is removed from the conductor quickly, and the falling edge is sharp.

When that device releases, nothing has been driven anywhere. The conductor is simply left connected to the supply through a resistor — and a conductor is not an abstract node. It is copper on a board, pins on packages, and the input structures of every attached device, all of which store charge. Collectively that is the bus's capacitance, and it has to be charged through the resistor before the conductor reaches the supply voltage.

So the rising edge is not an edge at all in the way the falling one is. It is a charging curve: current flows through the resistor into the bus capacitance, the voltage climbs, and the rate of climb falls off as the voltage approaches the supply. A receiving device does not see "HIGH" the instant the switch opens — it sees HIGH when the rising voltage crosses the threshold above which its input decides the line is high.

Three quantities therefore set how long a rising edge takes: the resistance, the total bus capacitance, and how far the voltage must climb before receivers agree it is HIGH. Increase the resistance and the charging current falls, so the climb is slower. Increase the capacitance — by adding devices, lengthening traces, or adding connectors — and there is more charge to move, so the climb is slower again.

3. The Same Release, Two Resistances

The figure isolates one variable. Both lines carry the same capacitance and are released at the same instant; only the resistance differs. The weaker pull-up delivers less charging current, so its line spends longer in transit and is recognised as HIGH later.

That delay is not cosmetic. The bus has a rhythm, and a line that has not finished rising has not yet conveyed anything to the devices reading it. If rising edges consume too much of the interval available, the bus cannot be operated as quickly as intended — the electrical choice has become a constraint on the protocol. Module 11 formalises this with the specification's actual limits; here the point is only that the connection exists.

4. Sizing Is a Range, Not a Value

Now the engineering question. Given a board, what resistance should be fitted?

The instinct is to make the pull-up strong — lower resistance, faster rise, more margin. That instinct runs into the opposite constraint immediately, and the two together are what make this a design problem rather than a lookup.

The upper bound comes from rise time. Too large a resistance means too little charging current for the capacitance present, so rising edges take too long and the bus cannot run at the intended rate. This bound tightens as the bus gets more capacitive — more devices, longer traces — and as the intended speed increases.

The lower bound comes from the pulling device. When a device holds the line LOW, all the current the resistor delivers flows through that device's switch to ground. A smaller resistance means more current. Two separate things object:

• The device must be able to sink it while still presenting a valid LOW. A device's output is specified to hold its output below some maximum LOW voltage while sinking up to some maximum current. Demand more than that and the device cannot hold the line low enough for receivers to read it as LOW — the bus fails in a way that looks like corrupted data rather than an electrical limit being exceeded.
• It is dissipated whenever the line is LOW. That current flows for as long as the line is held down, in every device that holds it, which matters for power-sensitive designs and for buses that spend a lot of time asserted.

So the resistance has a floor set by what the weakest attached device can sink, and a ceiling set by how fast the bus must rise given its capacitance. Any value between them is defensible; the correct answer is the range. A design that cannot find a value satisfying both bounds has a real problem — usually too much bus capacitance — and the fix is to reduce the load or split the bus, not to pick a compromise resistor and hope.

5. Deriving the Rise — From Charge to an Equation

§3 said the rising edge is a charging curve. That is worth deriving rather than asserted, because the equation that comes out of it is what turns "the bus is slow" into a number a designer can act on.

Follow the physics. At the instant every participant releases, the conductor sits near ground and the pull-up's full voltage appears across it, so current flows at its maximum. That current charges the bus capacitance, the conductor's voltage climbs — and as it climbs, the voltage across the resistor shrinks, so the current falls. Less current, slower climb. The rate of rise decays as the destination is approached, which is exactly the shape of a first-order exponential:

   V(t) = VDD x (1 - e^(-t / (R x C)))

Each symbol, precisely:

• V(t) — the conductor's voltage, measured from ground, at time t after release.
• VDD — the rail the pull-up connects to. This is the voltage the line is heading toward and, importantly, the voltage it never quite reaches.
• R — the pull-up resistance.
• C — the total bus capacitance on that conductor: every trace, pin and input structure added together. Chapter 2.6 breaks down where it comes from.
• R x C — the time constant, conventionally tau. It is a duration, and it is the only thing in the equation a designer controls.

Two readings of tau are worth memorising because they make estimation possible without a calculator. After one tau the line has covered about 63% of the way to VDD; after three, about 95%.

But the bus does not care about percentages of VDD. It cares about when a receiver decides the line is HIGH — a threshold, call it VTH. So rearrange for the time to reach it:

   t = -R x C x ln(1 - VTH / VDD)

That is the same equation solved for t, and it is the useful form. Read what it tells you:

• Time scales linearly with R and with C. Double either and the edge takes twice as long. This is why adding devices slows the bus without any component changing.
• The threshold enters logarithmically, through ln(1 - VTH/VDD). A threshold placed higher up the supply range costs disproportionately more time, because the line is climbing most slowly near the top.
• A threshold at VDD would take infinite time. The exponential never arrives, which is the mathematical statement of why an open-drain line's rising edge has a shape rather than an arrival.

One useful sanity anchor: for a threshold at 70% of VDD, -ln(1 - 0.7) is about 1.2, so the line reaches it in roughly 1.2 x R x C. A threshold at 30% takes about 0.36 x R x C. The interval between those two is about 0.85 x R x C — and that difference is the origin of the familiar 30%-to-70% rise-time convention, which exists precisely because measuring "when it arrives" is meaningless for a curve that never arrives. Measuring between two defined fractions is repeatable; measuring to the top is not.

6. Worked Examples

Four calculations, in the order an engineer actually meets them. Every number below is illustrative, chosen to make the arithmetic clear — none is a specification value, and §7 explains why no specification value appears in this chapter at all.

Example A — Given R and C, how long is the edge?

A bus has a 4.7 kilohm pull-up and an estimated 150 picofarads of total capacitance.

   tau = R x C
       = 4.7e3 x 150e-12
       = 705e-9 x ... = 0.705 microseconds     (approximately 700 ns)

   Time to 70% of VDD  =  1.2 x tau  =  approximately 850 ns
   Time from 30% to 70% =  0.85 x tau =  approximately 600 ns

Interpretation. Roughly 850 nanoseconds for a receiver with a threshold at 70% to see HIGH. Whether that is acceptable depends entirely on the bit period: it is a small fraction of a 10-microsecond bit and it is most of a 1-microsecond bit. The same edge is fine or fatal depending on the speed the bus runs at — which is why rise time is never judged in isolation.

Example B — Given a rise-time budget and C, what is the largest usable R?

A design must complete its rising edge within 300 nanoseconds, measured 30%-to-70%, with the same 150 picofarads.

   Required:   0.85 x R x C  <=  300 ns
               R  <=  300e-9 / (0.85 x 150e-12)
               R  <=  approximately 2.35 kilohm

Interpretation. A 4.7 kilohm pull-up cannot meet this budget at this loading; something around 2.2 kilohm can. Notice the shape of the result — the budget sets a ceiling on resistance. Every constraint that wants a faster edge pushes the resistance down.

Example C — Given the sink limit, what is the smallest usable R?

Suppose the weakest device on the bus is specified to hold its output below the required low level while sinking no more than 3 milliamps, on a 3.3 volt rail.

   Worst-case current through the pull-up while the line is held LOW:
       I  ~  VDD / R          (the LOW level is near ground, so almost all of
                               VDD appears across the resistor)

   Requirement:  VDD / R  <=  3 mA
                 R        >=  3.3 / 3e-3
                 R        >=  1.1 kilohm

Interpretation. A floor. Anything below about 1.1 kilohm demands more current than the weakest participant can sink while still presenting a valid LOW — and the failure mode is subtle: the bus does not stop, the LOW level simply rises until receivers stop reliably reading it as LOW, which looks like data corruption rather than an electrical limit being exceeded.

Examples B and C together are the design window. Roughly 1.1 kilohm to 2.35 kilohm for this board at this speed. Any value inside is defensible; the answer is the range, and choosing a value near the middle buys margin at both ends.

Example D — Add hardware, and watch the window close

Now three more devices and a short cable are added. Suppose that raises the total capacitance from 150 to 400 picofarads. Nothing else changes.

   New ceiling from the same 300 ns budget:
       R  <=  300e-9 / (0.85 x 400e-12)
       R  <=  approximately 880 ohm

   Floor from the same sink limit:  R  >=  1.1 kilohm

   880 ohm  <  1.1 kilohm   ->   THE WINDOW IS EMPTY

Interpretation, and this is the most valuable result in the chapter. There is no resistor that satisfies both constraints. The ceiling fell below the floor, so no value of R can give an edge fast enough without demanding more current than the weakest device can sink.

The instinct to "pick something in between and hope" produces a bus that fails intermittently. The correct conclusion is that the capacitance is the problem, and the resistor is not the variable that can fix it. The real options are to reduce the load (shorten the bus, drop the cable, move devices to a second bus segment), to relax the speed so the budget grows, or to change the devices so the floor moves. This is also why the specification places a ceiling on bus capacitance at all: past a certain loading the design window closes for everybody.

7. RTL Policy for This Chapter — and Why There Is No Synthesizable Model

A deliberate decision, stated plainly because its absence would otherwise look like an omission.

There is no synthesizable RTL in this chapter, and there should not be. An RC charging curve is analog behaviour produced by a resistor and distributed capacitance on a board. Synthesis creates logic; it does not create resistors, it does not create board capacitance, and no HDL construct describes an exponential voltage. Writing a delay statement that waits "one rise time" and calling it RTL would teach something false — that edge shape is a property of the design's logic rather than of the board it is soldered to.

What is legitimate is a simulation-only behavioural model, used when a testbench needs a released line to take realistic time to rise rather than snapping to HIGH instantly. One is worth showing, aggressively labelled:

   // PURPOSE: let a testbench see a rising edge that takes TIME, so a controller
   // that samples too early can actually be caught.
   //
   // THIS IS NOT RTL. It contains a delay, it models a board component, and no
   // synthesis tool can or should build it. It also does NOT reproduce an
   // exponential: it approximates the edge as "unknown for a while, then HIGH",
   // which is the honest digital abstraction of a curve crossing a threshold.
   module od_line_model #(
       parameter time T_RISE = 300ns,     // time from release to a valid HIGH
       parameter time T_FALL = 10ns       // pulling LOW is fast and actively driven
   )(
       input  logic a_low,
       input  logic b_low,
       output logic line                  // `logic`, not a net: this is a MODEL of
   );                                     //   a resolved line, not a resolved line
       wire any_low = a_low | b_low;      // wired-AND, as Chapter 2.5 develops

       always @(*) begin
           if (any_low) begin
               #(T_FALL) line = 1'b0;     // actively driven: sharp
           end else begin
               line = 1'bx;               // released: in transit, NOT yet HIGH --
               #(T_RISE) line = 1'b1;     //   a sampler that reads here gets X
           end
       end
   endmodule

Two things that model teaches which the equation cannot. A line in transit is neither LOW nor HIGH, and a design that samples during the climb reads something it should not trust — representing that interval as X makes such a bug fail loudly in simulation instead of passing by luck. And the asymmetry is visible in the parameters: T_FALL is small because a transistor drives it, T_RISE is large because a resistor does.

No Verilog or VHDL equivalent is given, and that is intentional. The construct would be the same delay-based abstraction in each language, teaching nothing new about the hardware — and this chapter's actual content is the derivation in §4 and the calculations in §5, which are language-independent. Adding two more copies of a non-synthesizable model purely for symmetry would pad the chapter and dilute the point. Executable tri-HDL returns in Chapter 2.5, where the wired-AND composition is a genuine logical behaviour worth modelling in all three.

8. Where Each Kind of Claim Actually Gets Verified

The chapter has now used three different kinds of statement — a protocol requirement, a device characteristic, and a board-dependent quantity — and a verification engineer needs to know that they are checked by completely different means. Conflating them produces both false confidence and wasted effort.

The practical lesson is the one designers most often miss: a fully passing RTL regression tells you nothing about rise time. In RTL simulation the line is an ideal logic value that transitions instantly, so every timing problem this chapter is about is invisible there. It is not that the regression is weak — it is measuring a different thing.

The reverse holds too. A beautiful oscilloscope capture proves the electrical layer is healthy and says nothing about whether the controller sequences a transfer correctly. The layers are complementary, and the one genuine overlap is the §6 behavioural model, which exists precisely to let a digital simulation ask "does my logic survive an edge that takes time?" — a question RTL simulation cannot otherwise pose.

9. Why the Pull-Up Is External

One more structural point, because it is frequently misunderstood.

The resistor is fitted on the board, not inside the devices. That is not an oversight or a cost saving. Its value has to be chosen against this board's capacitance, this supply voltage and this intended speed — quantities a device manufacturer cannot know. A device that supplied its own pull-up would also be imposing it on every other participant, and several devices each supplying one would combine into an unpredictably strong pull-up that the weakest device might be unable to sink.

Many parts do offer a weak internal pull-up intended for other purposes, and it is generally far too weak to serve here — the resulting rise times are long enough that the bus only works, if at all, at very low speeds with very little capacitance. Module 19.3 treats that comparison properly in an FPGA context. The architectural statement for now is simply that the restoring element is a board-level design decision, exactly one per line, and that leaving it out does not produce a bus that runs slowly — it produces a bus with no HIGH level at all.

10. Common Misconceptions

11. Reason It Through

Work this through before reading the answers.

A board works reliably with four devices on its I²C bus. Three more devices and a short ribbon cable are added, the pull-up resistors are left unchanged, and the bus now fails intermittently — more often at the higher of the two speeds the design supports.

What changed electrically? The bus capacitance. Three more device inputs, their package pins, extra trace length and a cable all add capacitance to the same conductors. Nothing about the resistors changed, but the load they must charge did.

Why does that produce failures? Because the same charging current now has more charge to move, so rising edges take longer. If a line has not crossed the receiver threshold by the time devices need to read it, what they read is wrong — and the failure presents as bad data rather than as an obviously electrical fault.

Why is it worse at the higher speed? Because faster operation shortens the interval available for a rising edge to complete, while the edge itself got slower. The two changes work against each other, which is why the slower mode can keep working while the faster one does not.

What are the candidate fixes, and what bounds them? Lowering the resistance restores charging current — but only until the current every device must sink while holding LOW exceeds what the weakest of them can take at a valid LOW voltage. If the required resistance falls below that floor, no resistor value works, and the honest fix is to reduce the load: shorten the bus, drop the cable, or split the devices across more than one bus. Note the shape of that answer, because it is the useful one: the range is fixed from two directions, and when it closes the problem is capacitance, not resistor selection.

12. Understanding Check

13. Summary

A resistor between each conductor and the positive supply restores a released line. When every device has released, it is the only path to anywhere and the conductor rises to HIGH; when any device is pulling, the strong switched path to ground dominates the weak resistor and the conductor is LOW.

The arrangement is deliberately asymmetric. LOW is actively driven through a low-impedance switch, so falling edges are sharp. HIGH is passively recovered by charging the bus capacitance — the traces, package pins and device inputs that are physically present — through a deliberately weak path, so rising edges take real, board-dependent time.

That makes the resistor a timing component. Rise duration is set by the resistance, the capacitance and how far the voltage must climb before receivers agree it is HIGH, so adding devices or lengthening the bus slows every rising edge without any component changing.

Sizing is therefore bounded from two directions: a ceiling set by rise time given the capacitance and intended speed, and a floor set by the current the weakest attached device can sink while still presenting a valid LOW. The answer is a range, not a value — and a board whose range has closed has a capacitance problem, not a resistor-selection problem.

The restoring element is external and board-level, one per line, because only the integrator knows the capacitance, supply and speed it must be chosen against. Omit it and the bus has no HIGH level at all.

14. What Comes Next

The node is now electrically complete: strong switched paths down, one weak permanent path up. Chapter 2.5 puts several devices on it at once and derives the behaviour that follows — any participant can assert the line, all must release it for it to rise, and a device that releases and looks can discover what everyone else is doing. That is the property the protocol's most distinctive mechanisms are built from.

Browse the full path on the I²C tutorials index.