tr, tf and Cb — The I²C Electrical Envelope

   // THE ELECTRICAL ENVELOPE: tr, tf and what they steal from the clock.
   //
   // Table 10:
   //     tr  rise time of both SDA and SCL   max 1000 / 300 / 120 ns
   //     tf  fall time of both SDA and SCL   max  300 / 300 / 120 ns
   //     Cb  capacitive load per bus line    max  400 / 400 / 550 pF
   //
   // THE FIRST THING TO SAY IS THAT A SINGLE DIGITAL SAMPLE CANNOT MEASURE AN EDGE RATE.
   // Every other block in this module works from `sda_in` and `scl_in` -- one bit each, the
   // output of an input buffer that has already decided high or low. An edge rate is the TIME
   // BETWEEN TWO VOLTAGE THRESHOLDS, and a one-bit sample has thrown that away before this
   // logic ever sees it. So this block takes TWO comparator outputs per line:
   //
   //     *_above_vil   the line is above the LOW threshold   (0.3 VDD)
   //     *_above_vih   the line is above the HIGH threshold  (0.7 VDD)
   //
   // and the rise time is the interval between those two crossings. That extra hardware is
   // the price of measuring an edge on-chip, and it is why compliance measurement is normally
   // done with a scope: a normal I2C input stage physically cannot report tr.
   //
   // WHY THE EDGES MATTER TO THE CLOCK. Table 10 contains an identity that is exact in all
   // three speed modes:
   //
   //     tLOW(min) + tHIGH(min) + tr(max) + tf(max) == 1 / fSCL(max)
   //
   //     Standard   4.7 + 4.0  + 1.000 + 0.300 = 10.0 us  = 1/100 kHz
   //     Fast       1.3 + 0.6  + 0.300 + 0.300 =  2.5 us  = 1/400 kHz
   //     Fm+        0.5 + 0.26 + 0.120 + 0.120 =  1.0 us  = 1/1000 kHz
   //
   // So the period is fully accounted for and the edges are part of the budget, not an
   // afterthought. Every nanosecond an edge takes beyond the assumed value has to come out of
   // a phase -- and since the phases have minima, a slow edge does not merely soften the
   // waveform, it eventually makes the clock illegal. This block therefore reports both the
   // measured edges AND the high time that survives them, which is the number a budget cares
   // about and the one Chapter 11.9 closes.
   //
   // Cb is not measurable here at all: capacitance is what CAUSES a slow edge, and this block
   // sees the consequence. Chapter 11.7 works the relationship the other way, from Cb and the
   // pull-up to the edge it produces.
   //
   // PASSIVE: observes comparator outputs and drives nothing.
   module i2c_edge_rate_monitor #(
       parameter int TICK_W = 16,
       // Fast-mode maxima, in ticks of a 100 MHz sample clock: 300 ns = 30 ticks each.
       parameter int T_R_MAX = 30,
       parameter int T_F_MAX = 30
   )(
       input  logic clk,
       input  logic rst_n,

       // Two thresholds per line. A conventional input stage provides only one of these;
       // measuring an edge requires the second.
       input  logic scl_above_vil,
       input  logic scl_above_vih,

       // ---- measured, on SCL ----
       output logic              edge_valid,      // pulse: an edge has been measured
       output logic              edge_was_rise,
       output logic [TICK_W-1:0] t_edge,

       // ---- verdicts ----
       output logic viol_tr,
       output logic viol_tf,

       // ---- the consequence for the clock ----
       // The high phase measured between the VIH crossings -- which is the time the line is
       // ACTUALLY above the high threshold, and therefore the tHIGH a receiver really gets.
       // A design that measured between the VIL crossings instead would report a longer high
       // phase than exists and would hide exactly the erosion this block is for.
       output logic              high_valid,
       output logic [TICK_W-1:0] t_high_effective,

       // ---- totals and worst cases: these are MAXIMA, so the worst case is the LARGEST ----
       output logic [TICK_W-1:0] n_rise,
       output logic [TICK_W-1:0] n_fall,
       output logic [TICK_W-1:0] n_viol,
       output logic [TICK_W-1:0] max_tr_seen,
       output logic [TICK_W-1:0] max_tf_seen
   );
       logic vil_q, vih_q;
       logic vil_rise, vil_fall, vih_rise, vih_fall;
       assign vil_rise = !vil_q &&  scl_above_vil;
       assign vil_fall =  vil_q && !scl_above_vil;
       assign vih_rise = !vih_q &&  scl_above_vih;
       assign vih_fall =  vih_q && !scl_above_vih;

       // A rising edge is timed from the VIL crossing to the VIH crossing; a falling edge from
       // the VIH crossing back down to the VIL crossing. Two timers, because a rise and a fall
       // can never be in flight at the same time but the arming conditions differ.
       logic              r_arm, f_arm;
       logic [TICK_W-1:0] e_ticks;
       logic [TICK_W-1:0] e_now;
       assign e_now = e_ticks + 1'b1;

       // The effective high time, measured VIH crossing to VIH crossing.
       logic              h_arm;
       logic [TICK_W-1:0] h_ticks;
       logic [TICK_W-1:0] h_now;
       assign h_now = h_ticks + 1'b1;

       always_ff @(posedge clk) begin
           if (!rst_n) begin
               vil_q            <= 1'b1;    // an idle bus is high, so above both thresholds
               vih_q            <= 1'b1;
               r_arm            <= 1'b0;
               f_arm            <= 1'b0;
               e_ticks          <= '0;
               h_arm            <= 1'b0;
               h_ticks          <= '0;
               edge_valid       <= 1'b0;
               edge_was_rise    <= 1'b0;
               t_edge           <= '0;
               viol_tr          <= 1'b0;
               viol_tf          <= 1'b0;
               high_valid       <= 1'b0;
               t_high_effective <= '0;
               n_rise           <= '0;
               n_fall           <= '0;
               n_viol           <= '0;
               max_tr_seen      <= '0;
               max_tf_seen      <= '0;
           end else begin
               vil_q <= scl_above_vil;
               vih_q <= scl_above_vih;

               edge_valid <= 1'b0;
               high_valid <= 1'b0;

               // ---- arm a RISE measurement when the line crosses the low threshold upward ----
               if (vil_rise) begin
                   r_arm   <= 1'b1;
                   f_arm   <= 1'b0;
                   e_ticks <= '0;
               // ---- arm a FALL measurement when it crosses the high threshold downward ----
               end else if (vih_fall) begin
                   f_arm   <= 1'b1;
                   r_arm   <= 1'b0;
                   e_ticks <= '0;
               end else if (r_arm && vih_rise) begin
                   // The rise completed: VIL to VIH.
                   r_arm         <= 1'b0;
                   edge_valid    <= 1'b1;
                   edge_was_rise <= 1'b1;
                   t_edge        <= e_now;
                   viol_tr       <= (e_now > T_R_MAX[TICK_W-1:0]);
                   viol_tf       <= 1'b0;
                   n_rise        <= n_rise + 1'b1;
                   if (e_now > T_R_MAX[TICK_W-1:0]) n_viol <= n_viol + 1'b1;
                   if (e_now > max_tr_seen) max_tr_seen <= e_now;
               end else if (f_arm && vil_fall) begin
                   // The fall completed: VIH down to VIL.
                   f_arm         <= 1'b0;
                   edge_valid    <= 1'b1;
                   edge_was_rise <= 1'b0;
                   t_edge        <= e_now;
                   viol_tf       <= (e_now > T_F_MAX[TICK_W-1:0]);
                   viol_tr       <= 1'b0;
                   n_fall        <= n_fall + 1'b1;
                   if (e_now > T_F_MAX[TICK_W-1:0]) n_viol <= n_viol + 1'b1;
                   if (e_now > max_tf_seen) max_tf_seen <= e_now;
               end else if (r_arm || f_arm) begin
                   e_ticks <= e_now;
               end

               // ---- the effective high time, VIH to VIH ----
               if (vih_rise) begin
                   h_arm   <= 1'b1;
                   h_ticks <= '0;
               end else if (h_arm && vih_fall) begin
                   h_arm            <= 1'b0;
                   high_valid       <= 1'b1;
                   t_high_effective <= h_now;
               end else if (h_arm) begin
                   h_ticks <= h_now;
               end
           end
       end
   endmodule

   `timescale 1ns/1ps
   // 100 MHz sample clock. Fast-mode tr(max) = tf(max) = 300 ns = 30 ticks.
   //
   // The stimulus drives the TWO THRESHOLD comparators directly, because that is the only way
   // an edge rate can be presented to logic. A slow edge is modelled as the two crossings
   // being far apart in time; a fast edge as them being close together. That is not an
   // approximation -- it is exactly what the comparators see.
   module i2c_edge_rate_monitor_tb;
       localparam int TICK_W  = 16;
       localparam int T_R_MAX = 30;
       // Deliberately DIFFERENT from T_R_MAX. Standard-mode's tr(max) and tf(max) differ by
       // more than 3x (1000 ns against 300 ns), so unequal limits are the realistic case -- and
       // with them equal, a design judging both against one limit is unobservable.
       localparam int T_F_MAX = 20;

       logic clk = 1'b0;
       always #5 clk = ~clk;

       logic rst_n = 1'b0;
       logic scl_above_vil = 1'b1, scl_above_vih = 1'b1;   // idle bus: above both thresholds

       logic edge_valid, edge_was_rise, viol_tr, viol_tf, high_valid;
       logic [TICK_W-1:0] t_edge, t_high_effective, n_rise, n_fall, n_viol;
       logic [TICK_W-1:0] max_tr_seen, max_tf_seen;

       int errors = 0;
       int base;
       logic [TICK_W-1:0] viol_before, nrise_before;
       logic [TICK_W-1:0] h_fast, h_slow;
       int hf, hs;

       i2c_edge_rate_monitor #(.TICK_W(TICK_W), .T_R_MAX(T_R_MAX), .T_F_MAX(T_F_MAX))
         dut (.*);

       initial begin #1000000; $display("FAIL: watchdog expired"); $finish; end

       logic [TICK_W-1:0] e_log [0:31];
       logic r_log [0:31];
       logic vr_log [0:31];
       logic vf_log [0:31];
       int n_log;
       always @(posedge clk) if (rst_n && edge_valid && n_log < 32) begin
           e_log[n_log] = t_edge;  r_log[n_log]  = edge_was_rise;
           vr_log[n_log] = viol_tr; vf_log[n_log] = viol_tf;
           n_log++;
       end

       logic [TICK_W-1:0] h_log [0:31];
       int n_hlog;
       always @(posedge clk) if (rst_n && high_valid && n_hlog < 32) begin
           h_log[n_hlog] = t_high_effective; n_hlog++;
       end

       task automatic tick(input int n);
           begin repeat (n) @(negedge clk); end
       endtask

       // A FALLING edge taking `tf` ticks: the line drops below VIH, then `tf` ticks later it
       // drops below VIL. Between the two it is in the undefined region.
       task automatic fall_edge(input int tf);
           begin
               scl_above_vih = 1'b0; tick(tf);
               scl_above_vil = 1'b0;
           end
       endtask

       // A RISING edge taking `tr` ticks: above VIL first, then above VIH `tr` ticks later.
       task automatic rise_edge(input int tr);
           begin
               scl_above_vil = 1'b1; tick(tr);
               scl_above_vih = 1'b1;
           end
       endtask

       // One SCL period with settable edge rates and phase widths. `hi` is the time spent
       // fully above VIH; the effective high time the block reports is that plus the sample
       // in which the crossing is observed.
       task automatic scl_period(input int tf, input int lo, input int tr, input int hi);
           begin
               fall_edge(tf);
               tick(lo);
               rise_edge(tr);
               tick(hi);
           end
       endtask

       initial begin
           tick(3);
           // These are MAXIMA, so the worst-case trackers start at zero.
           if (max_tr_seen !== '0 || max_tf_seen !== '0) begin
               $display("FAIL: the maximum trackers did not start at zero"); errors++; end
           rst_n = 1'b1; tick(2);
           scl_above_vil = 1'b1; scl_above_vih = 1'b1; tick(20);

           // ---- 1: FAST edges, well inside the limits. 10 ticks where 30 is the maximum.
           //      Nothing may be flagged -- for a maximum, smaller is safer.
           repeat (4) scl_period(10, 100, 10, 80);
           tick(20);
           if (n_viol !== '0) begin
               $display("FAIL: %0d fast edges flagged", n_viol); errors++; end
           if (n_rise < 16'd4 || n_fall < 16'd4) begin
               $display("FAIL: %0d rises and %0d falls measured from four periods",
                        n_rise, n_fall); errors++; end
           // The first edge measured is a FALL, because the stimulus starts from an idle high
           // bus. Getting the polarity right matters: a block that labelled it a rise would
           // then judge every edge against the wrong parameter.
           if (r_log[0] !== 1'b0) begin
               $display("FAIL: the first edge from an idle-high bus was labelled a RISE");
               errors++; end
           if (e_log[0] < 16'd8 || e_log[0] > 16'd12) begin
               $display("FAIL: a 10-tick fall measured %0d", e_log[0]); errors++; end

           // ---- 2: a SLOW RISE. 50 ticks where tr(max) is 30. Only the rise verdict fires.
           begin
               base = n_log;
               scl_period(10, 100, 50, 80);
               tick(20);
               // index base is the fall, base+1 the rise
               if (r_log[base + 1] !== 1'b1) begin
                   $display("FAIL: the second edge of a period should be the RISE"); errors++; end
               if (vr_log[base + 1] !== 1'b1) begin
                   $display("FAIL: a 50-tick rise was not flagged (tr max %0d)", T_R_MAX);
                   errors++; end
               if (vf_log[base + 1] !== 1'b0) begin
                   $display("FAIL: a slow RISE also flagged the FALL parameter"); errors++; end
               if (max_tr_seen < 16'd45) begin
                   $display("FAIL: max_tr_seen = %0d after a 50-tick rise", max_tr_seen);
                   errors++; end
           end

           // ---- 3: a SLOW FALL. The mirror -- tr and tf are separate parameters with
           //      separate limits, and in Standard-mode they differ by more than 3x, so a
           //      block that judged both against one limit would be wrong in Standard-mode
           //      even if it looked right in Fast-mode where the two happen to be equal.
           begin
               base = n_log;
               scl_period(60, 100, 10, 80);
               tick(20);
               if (vf_log[base] !== 1'b1) begin
                   $display("FAIL: a 60-tick fall was not flagged (tf max %0d)", T_F_MAX);
                   errors++; end
               if (vr_log[base] !== 1'b0) begin
                   $display("FAIL: a slow FALL also flagged the RISE parameter"); errors++; end
               if (max_tf_seen < 16'd55) begin
                   $display("FAIL: max_tf_seen = %0d after a 60-tick fall", max_tf_seen);
                   errors++; end
           end

           // ---- 3b: THE SEPARATION TEST. A 25-tick edge is LEGAL as a rise (max 30) and
           //      ILLEGAL as a fall (max 20). One duration, two verdicts, decided only by which
           //      parameter the edge is judged against.
           begin
               base = n_log;
               scl_period(25, 100, 25, 80);
               tick(20);
               if (vf_log[base] !== 1'b1) begin
                   $display("FAIL: a 25-tick FALL was not flagged against its own 20-tick limit -- both edges are being judged by one limit");
                   errors++; end
               if (vr_log[base + 1] !== 1'b0) begin
                   $display("FAIL: a 25-tick RISE was flagged against a 30-tick limit"); errors++; end
           end

           // ---- 4: BOUNDARIES. Exactly AT the maximum is legal; one tick above is not.
           begin
               base = n_log;
               scl_period(T_F_MAX, 100, T_R_MAX, 80);
               tick(20);
               if (vf_log[base] !== 1'b0) begin
                   $display("FAIL: a fall of EXACTLY tf(max) was rejected"); errors++; end
               if (vr_log[base + 1] !== 1'b0) begin
                   $display("FAIL: a rise of EXACTLY tr(max) was rejected"); errors++; end
           end
           begin
               base = n_log;
               scl_period(T_F_MAX + 1, 100, T_R_MAX + 1, 80);
               tick(20);
               if (vf_log[base] !== 1'b1) begin
                   $display("FAIL: a fall one tick above the maximum was accepted"); errors++; end
               if (vr_log[base + 1] !== 1'b1) begin
                   $display("FAIL: a rise one tick above the maximum was accepted"); errors++; end
           end

           // ---- 5: THE POINT OF THE BLOCK. The effective high time is measured between the
           //      VIH crossings, so it EXCLUDES the transition. Two periods asking for the
           //      same 80 ticks fully above VIH, one reached by a fast rise and one by a slow
           //      one, must report the SAME effective high time -- a VIL-based measurement
           //      would have included the rise and reported a much longer phase for the slow
           //      edge, hiding exactly the erosion this block exists to expose.
           //
           //      Each high phase is closed with an explicit falling edge before it is read.
           //      A high-phase measurement is reported by the fall that ENDS it, so reading
           //      the log straight after the period that opened it returns the PREVIOUS
           //      period's value -- which it did, before these tests were rewritten.
           begin
               scl_period(10, 100, 10, 80);
               fall_edge(10);                 // close the high phase so it is reported
               tick(20);
               h_fast = h_log[n_hlog - 1];

               scl_above_vil = 1'b1; tick(20);
               scl_period(10, 100, 60, 80);
               fall_edge(10);
               tick(20);
               h_slow = h_log[n_hlog - 1];

               if (h_slow > h_fast + 16'd10) begin
                   $display("FAIL: a 60-tick rise reported effective high %0d against %0d for a 10-tick rise -- the measurement is VIL-based, not VIH-based",
                            h_slow, h_fast); errors++; end
               if (h_fast < 16'd75 || h_fast > 16'd90) begin
                   $display("FAIL: an 80-tick fully-high interval measured %0d", h_fast);
                   errors++; end
           end

           // ---- 6: stated directly: an 80-tick high phase reached by a 40-tick rise must
           //      measure about 80, not 120.
           begin
               scl_above_vil = 1'b1; tick(20);
               scl_period(10, 100, 40, 80);
               fall_edge(10);
               tick(20);
               if (h_log[n_hlog - 1] > 16'd95) begin
                   $display("FAIL: the effective high time measured %0d with a 40-tick rise -- the transition was counted",
                            h_log[n_hlog - 1]); errors++; end
           end

           // ---- 7: an edge that never completes produces NO measurement. The line dips below
           //      VIH and comes back up without ever crossing VIL: that is noise on the high
           //      phase, not a falling edge, and timing it as one would report a fall that did
           //      not happen.
           begin
               nrise_before = n_fall;
               scl_above_vih = 1'b0; tick(20);
               scl_above_vih = 1'b1; tick(60);      // back up without crossing VIL
               if (n_fall !== nrise_before) begin
                   $display("FAIL: an incomplete edge produced %0d fall measurements",
                            n_fall - nrise_before); errors++; end
           end

           // ---- 8: a STATIC bus measures nothing. No threshold crossings, no edges.
           begin
               viol_before = n_viol; nrise_before = n_rise;
               scl_above_vil = 1'b1; scl_above_vih = 1'b1; tick(400);
               if (n_rise !== nrise_before || n_viol !== viol_before) begin
                   $display("FAIL: a static bus produced edges or violations"); errors++; end
           end

           if (errors == 0)
               $display("PASS: an edge rate needs two thresholds, tr and tf are separate maxima, the effective high time is VIH-based and excludes the transition, an incomplete edge is not an edge");
           else $display("FAIL: %0d error(s)", errors);
           $finish;
       end
   endmodule

   // THE ELECTRICAL ENVELOPE: tr, tf and what they steal from the clock.
   //
   // Table 10:
   //     tr  rise time of both SDA and SCL   max 1000 / 300 / 120 ns
   //     tf  fall time of both SDA and SCL   max  300 / 300 / 120 ns
   //     Cb  capacitive load per bus line    max  400 / 400 / 550 pF
   //
   // THE FIRST THING TO SAY IS THAT A SINGLE DIGITAL SAMPLE CANNOT MEASURE AN EDGE RATE.
   // Every other block in this module works from `sda_in` and `scl_in` -- one bit each, the
   // output of an input buffer that has already decided high or low. An edge rate is the TIME
   // BETWEEN TWO VOLTAGE THRESHOLDS, and a one-bit sample has thrown that away before this
   // logic ever sees it. So this block takes TWO comparator outputs per line:
   //
   //     *_above_vil   the line is above the LOW threshold   (0.3 VDD)
   //     *_above_vih   the line is above the HIGH threshold  (0.7 VDD)
   //
   // and the rise time is the interval between those two crossings. That extra hardware is
   // the price of measuring an edge on-chip, and it is why compliance measurement is normally
   // done with a scope: a normal I2C input stage physically cannot report tr.
   //
   // WHY THE EDGES MATTER TO THE CLOCK. Table 10 contains an identity that is exact in all
   // three speed modes:
   //
   //     tLOW(min) + tHIGH(min) + tr(max) + tf(max) == 1 / fSCL(max)
   //
   //     Standard   4.7 + 4.0  + 1.000 + 0.300 = 10.0 us  = 1/100 kHz
   //     Fast       1.3 + 0.6  + 0.300 + 0.300 =  2.5 us  = 1/400 kHz
   //     Fm+        0.5 + 0.26 + 0.120 + 0.120 =  1.0 us  = 1/1000 kHz
   //
   // So the period is fully accounted for and the edges are part of the budget, not an
   // afterthought. Every nanosecond an edge takes beyond the assumed value has to come out of
   // a phase -- and since the phases have minima, a slow edge does not merely soften the
   // waveform, it eventually makes the clock illegal. This block therefore reports both the
   // measured edges AND the high time that survives them, which is the number a budget cares
   // about and the one Chapter 11.9 closes.
   //
   // Cb is not measurable here at all: capacitance is what CAUSES a slow edge, and this block
   // sees the consequence. Chapter 11.7 works the relationship the other way, from Cb and the
   // pull-up to the edge it produces.
   //
   // PASSIVE: observes comparator outputs and drives nothing.
   // (Verilog-2001)
   module i2c_edge_rate_monitor #(
       parameter TICK_W = 16,
       // Fast-mode maxima, in ticks of a 100 MHz sample clock: 300 ns = 30 ticks each.
       parameter T_R_MAX = 30,
       parameter T_F_MAX = 30
   )(
       input  wire  clk,
       input  wire  rst_n,

       // Two thresholds per line. A conventional input stage provides only one of these;
       // measuring an edge requires the second.
       input  wire  scl_above_vil,
       input  wire  scl_above_vih,

       // ---- measured, on SCL ----
       output reg                edge_valid,      // pulse: an edge has been measured
       output reg                edge_was_rise,
       output reg   [TICK_W-1:0] t_edge,

       // ---- verdicts ----
       output reg   viol_tr,
       output reg   viol_tf,

       // ---- the consequence for the clock ----
       // The high phase measured between the VIH crossings -- which is the time the line is
       // ACTUALLY above the high threshold, and therefore the tHIGH a receiver really gets.
       // A design that measured between the VIL crossings instead would report a longer high
       // phase than exists and would hide exactly the erosion this block is for.
       output reg                high_valid,
       output reg   [TICK_W-1:0] t_high_effective,

       // ---- totals and worst cases: these are MAXIMA, so the worst case is the LARGEST ----
       output reg   [TICK_W-1:0] n_rise,
       output reg   [TICK_W-1:0] n_fall,
       output reg   [TICK_W-1:0] n_viol,
       output reg   [TICK_W-1:0] max_tr_seen,
       output reg   [TICK_W-1:0] max_tf_seen
   );
       reg vil_q, vih_q;
       wire vil_rise, vil_fall, vih_rise, vih_fall;
       assign vil_rise = !vil_q &&  scl_above_vil;
       assign vil_fall =  vil_q && !scl_above_vil;
       assign vih_rise = !vih_q &&  scl_above_vih;
       assign vih_fall =  vih_q && !scl_above_vih;

       // A rising edge is timed from the VIL crossing to the VIH crossing; a falling edge from
       // the VIH crossing back down to the VIL crossing. Two timers, because a rise and a fall
       // can never be in flight at the same time but the arming conditions differ.
       reg              r_arm, f_arm;
       reg [TICK_W-1:0] e_ticks;
       wire [TICK_W-1:0] e_now;
       assign e_now = e_ticks + 1'b1;

       // The effective high time, measured VIH crossing to VIH crossing.
       reg              h_arm;
       reg [TICK_W-1:0] h_ticks;
       wire [TICK_W-1:0] h_now;
       assign h_now = h_ticks + 1'b1;

       always @(posedge clk) begin
           if (!rst_n) begin
               vil_q            <= 1'b1;    // an idle bus is high, so above both thresholds
               vih_q            <= 1'b1;
               r_arm            <= 1'b0;
               f_arm            <= 1'b0;
               e_ticks          <= {TICK_W{1'b0}};
               h_arm            <= 1'b0;
               h_ticks          <= {TICK_W{1'b0}};
               edge_valid       <= 1'b0;
               edge_was_rise    <= 1'b0;
               t_edge           <= {TICK_W{1'b0}};
               viol_tr          <= 1'b0;
               viol_tf          <= 1'b0;
               high_valid       <= 1'b0;
               t_high_effective <= {TICK_W{1'b0}};
               n_rise           <= {TICK_W{1'b0}};
               n_fall           <= {TICK_W{1'b0}};
               n_viol           <= {TICK_W{1'b0}};
               max_tr_seen      <= {TICK_W{1'b0}};
               max_tf_seen      <= {TICK_W{1'b0}};
           end else begin
               vil_q <= scl_above_vil;
               vih_q <= scl_above_vih;

               edge_valid <= 1'b0;
               high_valid <= 1'b0;

               // ---- arm a RISE measurement when the line crosses the low threshold upward ----
               if (vil_rise) begin
                   r_arm   <= 1'b1;
                   f_arm   <= 1'b0;
                   e_ticks <= {TICK_W{1'b0}};
               // ---- arm a FALL measurement when it crosses the high threshold downward ----
               end else if (vih_fall) begin
                   f_arm   <= 1'b1;
                   r_arm   <= 1'b0;
                   e_ticks <= {TICK_W{1'b0}};
               end else if (r_arm && vih_rise) begin
                   // The rise completed: VIL to VIH.
                   r_arm         <= 1'b0;
                   edge_valid    <= 1'b1;
                   edge_was_rise <= 1'b1;
                   t_edge        <= e_now;
                   viol_tr       <= (e_now > T_R_MAX);
                   viol_tf       <= 1'b0;
                   n_rise        <= n_rise + 1'b1;
                   if (e_now > T_R_MAX) n_viol <= n_viol + 1'b1;
                   if (e_now > max_tr_seen) max_tr_seen <= e_now;
               end else if (f_arm && vil_fall) begin
                   // The fall completed: VIH down to VIL.
                   f_arm         <= 1'b0;
                   edge_valid    <= 1'b1;
                   edge_was_rise <= 1'b0;
                   t_edge        <= e_now;
                   viol_tf       <= (e_now > T_F_MAX);
                   viol_tr       <= 1'b0;
                   n_fall        <= n_fall + 1'b1;
                   if (e_now > T_F_MAX) n_viol <= n_viol + 1'b1;
                   if (e_now > max_tf_seen) max_tf_seen <= e_now;
               end else if (r_arm || f_arm) begin
                   e_ticks <= e_now;
               end

               // ---- the effective high time, VIH to VIH ----
               if (vih_rise) begin
                   h_arm   <= 1'b1;
                   h_ticks <= {TICK_W{1'b0}};
               end else if (h_arm && vih_fall) begin
                   h_arm            <= 1'b0;
                   high_valid       <= 1'b1;
                   t_high_effective <= h_now;
               end else if (h_arm) begin
                   h_ticks <= h_now;
               end
           end
       end
   endmodule

   `timescale 1ns/1ps
   // 100 MHz sample clock. Fast-mode tr(max) = tf(max) = 300 ns = 30 ticks.
   //
   // The stimulus drives the TWO THRESHOLD comparators directly, because that is the only way
   // an edge rate can be presented to logic. A slow edge is modelled as the two crossings
   // being far apart in time; a fast edge as them being close together. That is not an
   // approximation -- it is exactly what the comparators see.
   module i2c_edge_rate_monitor_tb;   // Verilog-2001
       localparam TICK_W  = 16;
       localparam T_R_MAX = 30;
       // Deliberately DIFFERENT from T_R_MAX. Standard-mode's tr(max) and tf(max) differ by
       // more than 3x (1000 ns against 300 ns), so unequal limits are the realistic case -- and
       // with them equal, a design judging both against one limit is unobservable.
       localparam T_F_MAX = 20;

       reg clk = 1'b0;
       always #5 clk = ~clk;

       reg rst_n = 1'b0;
       reg scl_above_vil = 1'b1, scl_above_vih = 1'b1;   // idle bus: above both thresholds

       wire edge_valid, edge_was_rise, viol_tr, viol_tf, high_valid;
       wire [TICK_W-1:0] t_edge, t_high_effective, n_rise, n_fall, n_viol;
       wire [TICK_W-1:0] max_tr_seen, max_tf_seen;

       integer errors = 0;
       integer base = 0;
       reg [TICK_W-1:0] viol_before, nrise_before;
       reg [TICK_W-1:0] h_fast, h_slow;
       integer hf = 0, hs = 0;

       i2c_edge_rate_monitor #(.TICK_W(TICK_W), .T_R_MAX(T_R_MAX), .T_F_MAX(T_F_MAX))
         dut (
           .clk(clk), .rst_n(rst_n), .scl_above_vil(scl_above_vil),
           .scl_above_vih(scl_above_vih), .edge_valid(edge_valid),
           .edge_was_rise(edge_was_rise), .t_edge(t_edge), .viol_tr(viol_tr), .viol_tf(viol_tf),
           .high_valid(high_valid), .t_high_effective(t_high_effective), .n_rise(n_rise),
           .n_fall(n_fall), .n_viol(n_viol), .max_tr_seen(max_tr_seen),
           .max_tf_seen(max_tf_seen));

       initial begin #1000000; $display("FAIL: watchdog expired"); $finish; end

       reg [TICK_W-1:0] e_log [0:31];
       reg r_log [0:31];
       reg vr_log [0:31];
       reg vf_log [0:31];
       integer n_log = 0;
       always @(posedge clk) if (rst_n && edge_valid && n_log < 32) begin
           e_log[n_log] = t_edge;  r_log[n_log]  = edge_was_rise;
           vr_log[n_log] = viol_tr; vf_log[n_log] = viol_tf;
           n_log = n_log + 1;
       end

       reg [TICK_W-1:0] h_log [0:31];
       integer n_hlog = 0;
       always @(posedge clk) if (rst_n && high_valid && n_hlog < 32) begin
           h_log[n_hlog] = t_high_effective; n_hlog = n_hlog + 1;
       end

       task tick;
           input integer n;
       begin repeat (n) @(negedge clk);     end
       endtask

       // A FALLING edge taking `tf` ticks: the line drops below VIH, then `tf` ticks later it
       // drops below VIL. Between the two it is in the undefined region.
       task fall_edge;
           input integer tf;
       begin
               scl_above_vih = 1'b0; tick(tf);
               scl_above_vil = 1'b0;
               end
       endtask

       // A RISING edge taking `tr` ticks: above VIL first, then above VIH `tr` ticks later.
       task rise_edge;
           input integer tr;
       begin
               scl_above_vil = 1'b1; tick(tr);
               scl_above_vih = 1'b1;
               end
       endtask

       // One SCL period with settable edge rates and phase widths. `hi` is the time spent
       // fully above VIH; the effective high time the block reports is that plus the sample
       // in which the crossing is observed.
       task scl_period;
           input integer tf;
           input integer lo;
           input integer tr;
           input integer hi;
       begin
               fall_edge(tf);
               tick(lo);
               rise_edge(tr);
               tick(hi);
               end
       endtask

       initial begin
           tick(3);
           // These are MAXIMA, so the worst-case trackers start at zero.
           if (max_tr_seen !== {TICK_W{1'b0}} || max_tf_seen !== {TICK_W{1'b0}}) begin
               $display("FAIL: the maximum trackers did not start at zero"); errors = errors + 1; end
           rst_n = 1'b1; tick(2);
           scl_above_vil = 1'b1; scl_above_vih = 1'b1; tick(20);

           // ---- 1: FAST edges, well inside the limits. 10 ticks where 30 is the maximum.
           //      Nothing may be flagged -- for a maximum, smaller is safer.
           repeat (4) scl_period(10, 100, 10, 80);
           tick(20);
           if (n_viol !== {TICK_W{1'b0}}) begin
               $display("FAIL: %0d fast edges flagged", n_viol); errors = errors + 1; end
           if (n_rise < 16'd4 || n_fall < 16'd4) begin
               $display("FAIL: %0d rises and %0d falls measured from four periods",
                        n_rise, n_fall); errors = errors + 1; end
           // The first edge measured is a FALL, because the stimulus starts from an idle high
           // bus. Getting the polarity right matters: a block that labelled it a rise would
           // then judge every edge against the wrong parameter.
           if (r_log[0] !== 1'b0) begin
               $display("FAIL: the first edge from an idle-high bus was labelled a RISE");
               errors = errors + 1; end
           if (e_log[0] < 16'd8 || e_log[0] > 16'd12) begin
               $display("FAIL: a 10-tick fall measured %0d", e_log[0]); errors = errors + 1; end

           // ---- 2: a SLOW RISE. 50 ticks where tr(max) is 30. Only the rise verdict fires.
           begin
               base = n_log;
               scl_period(10, 100, 50, 80);
               tick(20);
               // index base is the fall, base+1 the rise
               if (r_log[base + 1] !== 1'b1) begin
                   $display("FAIL: the second edge of a period should be the RISE"); errors = errors + 1; end
               if (vr_log[base + 1] !== 1'b1) begin
                   $display("FAIL: a 50-tick rise was not flagged (tr max %0d)", T_R_MAX);
                   errors = errors + 1; end
               if (vf_log[base + 1] !== 1'b0) begin
                   $display("FAIL: a slow RISE also flagged the FALL parameter"); errors = errors + 1; end
               if (max_tr_seen < 16'd45) begin
                   $display("FAIL: max_tr_seen = %0d after a 50-tick rise", max_tr_seen);
                   errors = errors + 1; end
           end

           // ---- 3: a SLOW FALL. The mirror -- tr and tf are separate parameters with
           //      separate limits, and in Standard-mode they differ by more than 3x, so a
           //      block that judged both against one limit would be wrong in Standard-mode
           //      even if it looked right in Fast-mode where the two happen to be equal.
           begin
               base = n_log;
               scl_period(60, 100, 10, 80);
               tick(20);
               if (vf_log[base] !== 1'b1) begin
                   $display("FAIL: a 60-tick fall was not flagged (tf max %0d)", T_F_MAX);
                   errors = errors + 1; end
               if (vr_log[base] !== 1'b0) begin
                   $display("FAIL: a slow FALL also flagged the RISE parameter"); errors = errors + 1; end
               if (max_tf_seen < 16'd55) begin
                   $display("FAIL: max_tf_seen = %0d after a 60-tick fall", max_tf_seen);
                   errors = errors + 1; end
           end

           // ---- 3b: THE SEPARATION TEST. A 25-tick edge is LEGAL as a rise (max 30) and
           //      ILLEGAL as a fall (max 20). One duration, two verdicts, decided only by which
           //      parameter the edge is judged against.
           begin
               base = n_log;
               scl_period(25, 100, 25, 80);
               tick(20);
               if (vf_log[base] !== 1'b1) begin
                   $display("FAIL: a 25-tick FALL was not flagged against its own 20-tick limit -- both edges are being judged by one limit");
                   errors = errors + 1; end
               if (vr_log[base + 1] !== 1'b0) begin
                   $display("FAIL: a 25-tick RISE was flagged against a 30-tick limit"); errors = errors + 1; end
           end

           // ---- 4: BOUNDARIES. Exactly AT the maximum is legal; one tick above is not.
           begin
               base = n_log;
               scl_period(T_F_MAX, 100, T_R_MAX, 80);
               tick(20);
               if (vf_log[base] !== 1'b0) begin
                   $display("FAIL: a fall of EXACTLY tf(max) was rejected"); errors = errors + 1; end
               if (vr_log[base + 1] !== 1'b0) begin
                   $display("FAIL: a rise of EXACTLY tr(max) was rejected"); errors = errors + 1; end
           end
           begin
               base = n_log;
               scl_period(T_F_MAX + 1, 100, T_R_MAX + 1, 80);
               tick(20);
               if (vf_log[base] !== 1'b1) begin
                   $display("FAIL: a fall one tick above the maximum was accepted"); errors = errors + 1; end
               if (vr_log[base + 1] !== 1'b1) begin
                   $display("FAIL: a rise one tick above the maximum was accepted"); errors = errors + 1; end
           end

           // ---- 5: THE POINT OF THE BLOCK. The effective high time is measured between the
           //      VIH crossings, so it EXCLUDES the transition. Two periods asking for the
           //      same 80 ticks fully above VIH, one reached by a fast rise and one by a slow
           //      one, must report the SAME effective high time -- a VIL-based measurement
           //      would have included the rise and reported a much longer phase for the slow
           //      edge, hiding exactly the erosion this block exists to expose.
           //
           //      Each high phase is closed with an explicit falling edge before it is read.
           //      A high-phase measurement is reported by the fall that ENDS it, so reading
           //      the log straight after the period that opened it returns the PREVIOUS
           //      period's value -- which it did, before these tests were rewritten.
           begin
               scl_period(10, 100, 10, 80);
               fall_edge(10);                 // close the high phase so it is reported
               tick(20);
               h_fast = h_log[n_hlog - 1];

               scl_above_vil = 1'b1; tick(20);
               scl_period(10, 100, 60, 80);
               fall_edge(10);
               tick(20);
               h_slow = h_log[n_hlog - 1];

               if (h_slow > h_fast + 16'd10) begin
                   $display("FAIL: a 60-tick rise reported effective high %0d against %0d for a 10-tick rise -- the measurement is VIL-based, not VIH-based",
                            h_slow, h_fast); errors = errors + 1; end
               if (h_fast < 16'd75 || h_fast > 16'd90) begin
                   $display("FAIL: an 80-tick fully-high interval measured %0d", h_fast);
                   errors = errors + 1; end
           end

           // ---- 6: stated directly: an 80-tick high phase reached by a 40-tick rise must
           //      measure about 80, not 120.
           begin
               scl_above_vil = 1'b1; tick(20);
               scl_period(10, 100, 40, 80);
               fall_edge(10);
               tick(20);
               if (h_log[n_hlog - 1] > 16'd95) begin
                   $display("FAIL: the effective high time measured %0d with a 40-tick rise -- the transition was counted",
                            h_log[n_hlog - 1]); errors = errors + 1; end
           end

           // ---- 7: an edge that never completes produces NO measurement. The line dips below
           //      VIH and comes back up without ever crossing VIL: that is noise on the high
           //      phase, not a falling edge, and timing it as one would report a fall that did
           //      not happen.
           begin
               nrise_before = n_fall;
               scl_above_vih = 1'b0; tick(20);
               scl_above_vih = 1'b1; tick(60);      // back up without crossing VIL
               if (n_fall !== nrise_before) begin
                   $display("FAIL: an incomplete edge produced %0d fall measurements",
                            n_fall - nrise_before); errors = errors + 1; end
           end

           // ---- 8: a STATIC bus measures nothing. No threshold crossings, no edges.
           begin
               viol_before = n_viol; nrise_before = n_rise;
               scl_above_vil = 1'b1; scl_above_vih = 1'b1; tick(400);
               if (n_rise !== nrise_before || n_viol !== viol_before) begin
                   $display("FAIL: a static bus produced edges or violations"); errors = errors + 1; end
           end

           if (errors == 0)
               $display("PASS: an edge rate needs two thresholds, tr and tf are separate maxima, the effective high time is VIH-based and excludes the transition, an incomplete edge is not an edge");
           else $display("FAIL: %0d error(s)", errors);
           $finish;
       end
   endmodule

   library ieee;
   use ieee.std_logic_1164.all;
   use ieee.numeric_std.all;

   -- THE ELECTRICAL ENVELOPE: tr, tf and what they steal from the clock.
   --
   -- Table 10:
   --     tr  rise time of both SDA and SCL   max 1000 / 300 / 120 ns
   --     tf  fall time of both SDA and SCL   max  300 / 300 / 120 ns
   --     Cb  capacitive load per bus line    max  400 / 400 / 550 pF
   --
   -- A SINGLE DIGITAL SAMPLE CANNOT MEASURE AN EDGE RATE. Every other block in this module works
   -- from sda_in and scl_in -- one bit each, the output of an input buffer that has already decided
   -- high or low. An edge rate is the TIME BETWEEN TWO VOLTAGE THRESHOLDS, and a one-bit sample has
   -- thrown that away before this logic ever sees it. So this block takes TWO comparator outputs:
   --
   --     *_above_vil   the line is above the LOW threshold   (0.3 VDD)
   --     *_above_vih   the line is above the HIGH threshold  (0.7 VDD)
   --
   -- and the rise time is the interval between those two crossings. That extra hardware is the
   -- price of measuring an edge on-chip, and it is why compliance measurement is normally done with
   -- a scope: a normal I2C input stage physically cannot report tr.
   --
   -- WHY THE EDGES MATTER TO THE CLOCK. Table 10 contains an identity exact in all three modes:
   --
   --     tLOW(min) + tHIGH(min) + tr(max) + tf(max) == 1 / fSCL(max)
   --
   --     Standard   4.7 + 4.0  + 1.000 + 0.300 = 10.0 us = 1/100 kHz
   --     Fast       1.3 + 0.6  + 0.300 + 0.300 =  2.5 us = 1/400 kHz
   --     Fm+        0.5 + 0.26 + 0.120 + 0.120 =  1.0 us = 1/1000 kHz
   --
   -- So the period is fully accounted for and the edges are part of the budget, not an afterthought.
   -- Every nanosecond an edge takes beyond the assumed value comes out of a phase -- and since the
   -- phases have minima, a slow edge does not merely soften the waveform, it eventually makes the
   -- clock illegal. This block therefore reports both the measured edges AND the high time that
   -- survives them, which is the number Chapter 11.9 closes a budget with.
   --
   -- Cb is not measurable here at all: capacitance CAUSES a slow edge, and this block sees the
   -- consequence. Chapter 11.7 works the relationship the other way, from Cb and the pull-up.
   entity i2c_edge_rate_monitor is
       generic (
           TICK_W : positive := 16;
           -- Fast-mode maxima, in ticks of a 100 MHz sample clock: 300 ns = 30 ticks each.
           T_R_MAX : natural := 30;
           T_F_MAX : natural := 30
       );
       port (
           clk   : in std_logic;
           rst_n : in std_logic;

           -- Two thresholds. A conventional input stage provides only one of these.
           scl_above_vil : in std_logic;
           scl_above_vih : in std_logic;

           edge_valid    : out std_logic;
           edge_was_rise : out std_logic;
           t_edge        : out unsigned(TICK_W - 1 downto 0);

           viol_tr : out std_logic;
           viol_tf : out std_logic;

           -- The high phase measured between the VIH crossings -- the time the line is ACTUALLY
           -- above the high threshold, and therefore the tHIGH a receiver really gets. Measuring
           -- between the VIL crossings instead would report a longer high phase than exists and
           -- would hide exactly the erosion this block is for.
           high_valid       : out std_logic;
           t_high_effective : out unsigned(TICK_W - 1 downto 0);

           -- These are MAXIMA, so the worst case is the LARGEST value seen.
           n_rise : out unsigned(TICK_W - 1 downto 0);
           n_fall : out unsigned(TICK_W - 1 downto 0);
           n_viol : out unsigned(TICK_W - 1 downto 0);
           max_tr_seen : out unsigned(TICK_W - 1 downto 0);
           max_tf_seen : out unsigned(TICK_W - 1 downto 0)
       );
   end entity;

   architecture rtl of i2c_edge_rate_monitor is
       signal vil_q, vih_q : std_logic := '1';   -- an idle bus is high, so above both thresholds
       signal vil_rise, vil_fall, vih_rise, vih_fall : std_logic;

       -- A rising edge is timed from the VIL crossing to the VIH crossing; a falling edge from the
       -- VIH crossing back down to the VIL crossing. Two arming conditions, one timer, because a
       -- rise and a fall can never be in flight at the same time.
       signal r_arm, f_arm : std_logic := '0';
       signal e_ticks : unsigned(TICK_W - 1 downto 0) := (others => '0');
       signal e_now   : unsigned(TICK_W - 1 downto 0);

       -- The effective high time, measured VIH crossing to VIH crossing.
       signal h_arm   : std_logic := '0';
       signal h_ticks : unsigned(TICK_W - 1 downto 0) := (others => '0');
       signal h_now   : unsigned(TICK_W - 1 downto 0);
   begin
       vil_rise <= (not vil_q) and scl_above_vil;
       vil_fall <= vil_q and (not scl_above_vil);
       vih_rise <= (not vih_q) and scl_above_vih;
       vih_fall <= vih_q and (not scl_above_vih);

       e_now <= e_ticks + 1;
       h_now <= h_ticks + 1;

       process (clk)
       begin
           if rising_edge(clk) then
               if rst_n = '0' then
                   vil_q            <= '1';
                   vih_q            <= '1';
                   r_arm            <= '0';
                   f_arm            <= '0';
                   e_ticks          <= (others => '0');
                   h_arm            <= '0';
                   h_ticks          <= (others => '0');
                   edge_valid       <= '0';
                   edge_was_rise    <= '0';
                   t_edge           <= (others => '0');
                   viol_tr          <= '0';
                   viol_tf          <= '0';
                   high_valid       <= '0';
                   t_high_effective <= (others => '0');
                   n_rise           <= (others => '0');
                   n_fall           <= (others => '0');
                   n_viol           <= (others => '0');
                   max_tr_seen      <= (others => '0');
                   max_tf_seen      <= (others => '0');
               else
                   vil_q <= scl_above_vil;
                   vih_q <= scl_above_vih;

                   edge_valid <= '0';
                   high_valid <= '0';

                   -- arm a RISE measurement when the line crosses the low threshold upward
                   if vil_rise = '1' then
                       r_arm   <= '1';
                       f_arm   <= '0';
                       e_ticks <= (others => '0');
                   -- arm a FALL measurement when it crosses the high threshold downward
                   elsif vih_fall = '1' then
                       f_arm   <= '1';
                       r_arm   <= '0';
                       e_ticks <= (others => '0');
                   elsif r_arm = '1' and vih_rise = '1' then
                       -- The rise completed: VIL to VIH.
                       r_arm         <= '0';
                       edge_valid    <= '1';
                       edge_was_rise <= '1';
                       t_edge        <= e_now;
                       viol_tf       <= '0';
                       if e_now > to_unsigned(T_R_MAX, TICK_W) then
                           viol_tr <= '1';
                           n_viol  <= n_viol + 1;
                       else
                           viol_tr <= '0';
                       end if;
                       n_rise <= n_rise + 1;
                       if e_now > max_tr_seen then max_tr_seen <= e_now; end if;
                   elsif f_arm = '1' and vil_fall = '1' then
                       -- The fall completed: VIH down to VIL.
                       f_arm         <= '0';
                       edge_valid    <= '1';
                       edge_was_rise <= '0';
                       t_edge        <= e_now;
                       viol_tr       <= '0';
                       if e_now > to_unsigned(T_F_MAX, TICK_W) then
                           viol_tf <= '1';
                           n_viol  <= n_viol + 1;
                       else
                           viol_tf <= '0';
                       end if;
                       n_fall <= n_fall + 1;
                       if e_now > max_tf_seen then max_tf_seen <= e_now; end if;
                   elsif r_arm = '1' or f_arm = '1' then
                       e_ticks <= e_now;
                   end if;

                   -- the effective high time, VIH to VIH
                   if vih_rise = '1' then
                       h_arm   <= '1';
                       h_ticks <= (others => '0');
                   elsif h_arm = '1' and vih_fall = '1' then
                       h_arm            <= '0';
                       high_valid       <= '1';
                       t_high_effective <= h_now;
                   elsif h_arm = '1' then
                       h_ticks <= h_now;
                   end if;
               end if;
           end if;
       end process;
   end architecture;

   library ieee;
   use ieee.std_logic_1164.all;
   use ieee.numeric_std.all;

   -- 100 MHz sample clock. Fast-mode tr(max) = tf(max) = 300 ns = 30 ticks.
   --
   -- The stimulus drives the TWO THRESHOLD comparators directly, because that is the only way an
   -- edge rate can be presented to logic. A slow edge is the two crossings far apart in time; a
   -- fast edge is them close together. Not an approximation -- exactly what the comparators see.
   entity i2c_edge_rate_monitor_tb is
   end entity;

   architecture sim of i2c_edge_rate_monitor_tb is
       constant TICK_W  : positive := 16;
       constant T_R_MAX : natural  := 30;
       -- Deliberately DIFFERENT from T_R_MAX. Standard-mode's tr(max) and tf(max) differ by more
       -- than 3x (1000 ns against 300 ns), so unequal limits are the realistic case -- and with them
       -- equal, a design judging both against one limit is unobservable.
       constant T_F_MAX : natural  := 20;

       signal clk   : std_logic := '0';
       signal rst_n : std_logic := '0';
       signal scl_above_vil, scl_above_vih : std_logic := '1';   -- idle: above both thresholds

       signal edge_valid, edge_was_rise, viol_tr, viol_tf, high_valid : std_logic;
       signal t_edge, t_high_effective : unsigned(TICK_W - 1 downto 0);
       signal n_rise, n_fall, n_viol : unsigned(TICK_W - 1 downto 0);
       signal max_tr_seen, max_tf_seen : unsigned(TICK_W - 1 downto 0);

       type tick_arr is array (0 to 31) of unsigned(TICK_W - 1 downto 0);
       type bit_arr  is array (0 to 31) of std_logic;
       signal e_log, h_log : tick_arr := (others => (others => '0'));
       signal r_log, vr_log, vf_log : bit_arr := (others => '0');
       signal n_log, n_hlog : natural := 0;

       signal test_done : std_logic := '0';
   begin
       dut : entity work.i2c_edge_rate_monitor
           generic map (TICK_W => TICK_W, T_R_MAX => T_R_MAX, T_F_MAX => T_F_MAX)
           port map (clk => clk, rst_n => rst_n, scl_above_vil => scl_above_vil,
                     scl_above_vih => scl_above_vih, edge_valid => edge_valid,
                     edge_was_rise => edge_was_rise, t_edge => t_edge, viol_tr => viol_tr,
                     viol_tf => viol_tf, high_valid => high_valid,
                     t_high_effective => t_high_effective, n_rise => n_rise, n_fall => n_fall,
                     n_viol => n_viol, max_tr_seen => max_tr_seen, max_tf_seen => max_tf_seen);

       clk <= not clk after 5 ns;

       watchdog : process
       begin
           wait for 1 ms;
           if test_done = '0' then report "watchdog expired" severity failure; end if;
           wait;
       end process;

       obs_e : process (clk)
       begin
           if rising_edge(clk) and rst_n = '1' and edge_valid = '1' and n_log < 32 then
               e_log(n_log) <= t_edge;  r_log(n_log)  <= edge_was_rise;
               vr_log(n_log) <= viol_tr; vf_log(n_log) <= viol_tf;
               n_log <= n_log + 1;
           end if;
       end process;

       obs_h : process (clk)
       begin
           if rising_edge(clk) and rst_n = '1' and high_valid = '1' and n_hlog < 32 then
               h_log(n_hlog) <= t_high_effective; n_hlog <= n_hlog + 1;
           end if;
       end process;

       stim : process
           variable errs : natural := 0;
           variable base : natural;
           variable h_fast, h_slow : unsigned(TICK_W - 1 downto 0);
           variable viol_before, nfall_before, nrise_before : unsigned(TICK_W - 1 downto 0);

           procedure tick (n : in positive) is
           begin
               for i in 1 to n loop wait until falling_edge(clk); end loop;
           end procedure;

           -- A FALLING edge taking `tf` ticks: below VIH, then `tf` ticks later below VIL.
           procedure fall_edge (tf : in positive) is
           begin
               scl_above_vih <= '0'; tick(tf);
               scl_above_vil <= '0';
           end procedure;

           -- A RISING edge taking `tr` ticks: above VIL first, then above VIH `tr` ticks later.
           procedure rise_edge (tr : in positive) is
           begin
               scl_above_vil <= '1'; tick(tr);
               scl_above_vih <= '1';
           end procedure;

           procedure scl_period (tf, lo, tr, hi : in positive) is
           begin
               fall_edge(tf);
               tick(lo);
               rise_edge(tr);
               tick(hi);
           end procedure;
       begin
           tick(3);
           -- These are MAXIMA, so the worst-case trackers start at zero.
           if max_tr_seen /= to_unsigned(0, TICK_W) or max_tf_seen /= to_unsigned(0, TICK_W) then
               report "the maximum trackers did not start at zero" severity error;
               errs := errs + 1; end if;
           rst_n <= '1'; tick(2);
           scl_above_vil <= '1'; scl_above_vih <= '1'; tick(20);

           -- 1: FAST edges, well inside the limits. 10 ticks where 30 is the maximum. Nothing may
           -- be flagged -- for a maximum, smaller is safer.
           for i in 1 to 4 loop scl_period(10, 100, 10, 80); end loop;
           tick(20);
           if n_viol /= to_unsigned(0, TICK_W) then
               report "fast edges were flagged" severity error; errs := errs + 1; end if;
           if n_rise < to_unsigned(4, TICK_W) or n_fall < to_unsigned(4, TICK_W) then
               report "too few edges measured from four periods" severity error;
               errs := errs + 1; end if;
           -- The first edge is a FALL, because the stimulus starts from an idle high bus. Getting
           -- the polarity right matters: a block labelling it a rise would judge every edge against
           -- the wrong parameter.
           if r_log(0) /= '0' then
               report "the first edge from an idle-high bus was labelled a RISE" severity error;
               errs := errs + 1; end if;
           if e_log(0) < to_unsigned(8, TICK_W) or e_log(0) > to_unsigned(12, TICK_W) then
               report "a 10-tick fall measured out of range" severity error; errs := errs + 1; end if;

           -- 2: a SLOW RISE. 50 ticks where tr(max) is 30. Only the rise verdict fires.
           base := n_log;
           scl_period(10, 100, 50, 80);
           tick(20);
           if r_log(base + 1) /= '1' then
               report "the second edge of a period should be the RISE" severity error;
               errs := errs + 1; end if;
           if vr_log(base + 1) /= '1' then
               report "a 50-tick rise was not flagged" severity error; errs := errs + 1; end if;
           if vf_log(base + 1) /= '0' then
               report "a slow RISE also flagged the FALL parameter" severity error;
               errs := errs + 1; end if;
           if max_tr_seen < to_unsigned(45, TICK_W) then
               report "the rise worst case did not move" severity error; errs := errs + 1; end if;

           -- 3: a SLOW FALL. The mirror -- tr and tf are separate parameters with separate limits,
           -- and in Standard-mode they differ by more than 3x, so a block judging both against one
           -- limit would be wrong in Standard-mode even if it looked right in Fast-mode where the
           -- two happen to be equal.
           base := n_log;
           scl_period(60, 100, 10, 80);
           tick(20);
           if vf_log(base) /= '1' then
               report "a 60-tick fall was not flagged" severity error; errs := errs + 1; end if;
           if vr_log(base) /= '0' then
               report "a slow FALL also flagged the RISE parameter" severity error;
               errs := errs + 1; end if;
           if max_tf_seen < to_unsigned(55, TICK_W) then
               report "the fall worst case did not move" severity error; errs := errs + 1; end if;

           -- 3b: THE SEPARATION TEST. A 25-tick edge is LEGAL as a rise (max 30) and ILLEGAL as a
           -- fall (max 20). One duration, two verdicts, decided only by which parameter it is
           -- judged against.
           base := n_log;
           scl_period(25, 100, 25, 80);
           tick(20);
           if vf_log(base) /= '1' then
               report "a 25-tick FALL was not flagged against its own 20-tick limit -- both edges "
                    & "are being judged by one limit" severity error; errs := errs + 1; end if;
           if vr_log(base + 1) /= '0' then
               report "a 25-tick RISE was flagged against a 30-tick limit" severity error;
               errs := errs + 1; end if;

           -- 4: BOUNDARIES. Exactly AT the maximum is legal; one tick above is not.
           base := n_log;
           scl_period(T_F_MAX, 100, T_R_MAX, 80);
           tick(20);
           if vf_log(base) /= '0' then
               report "a fall of EXACTLY tf(max) was rejected" severity error; errs := errs + 1; end if;
           if vr_log(base + 1) /= '0' then
               report "a rise of EXACTLY tr(max) was rejected" severity error; errs := errs + 1; end if;

           base := n_log;
           scl_period(T_F_MAX + 1, 100, T_R_MAX + 1, 80);
           tick(20);
           if vf_log(base) /= '1' then
               report "a fall one tick above the maximum was accepted" severity error;
               errs := errs + 1; end if;
           if vr_log(base + 1) /= '1' then
               report "a rise one tick above the maximum was accepted" severity error;
               errs := errs + 1; end if;

           -- 5: THE POINT OF THE BLOCK. The effective high time is measured between the VIH
           -- crossings, so it EXCLUDES the transition. Two periods asking for the same 80 ticks
           -- fully above VIH, one reached by a fast rise and one by a slow one, must report the
           -- SAME effective high time -- a VIL-based measurement would have included the rise and
           -- reported a much longer phase for the slow edge, hiding the erosion this block exposes.
           --
           -- Each high phase is closed with an explicit falling edge before it is read: a
           -- high-phase measurement is reported by the fall that ENDS it, so reading the log
           -- straight after the period that opened it returns the PREVIOUS period's value.
           scl_period(10, 100, 10, 80);
           fall_edge(10);
           tick(20);
           h_fast := h_log(n_hlog - 1);

           scl_above_vil <= '1'; tick(20);
           scl_period(10, 100, 60, 80);
           fall_edge(10);
           tick(20);
           h_slow := h_log(n_hlog - 1);

           if h_slow > h_fast + 10 then
               report "the slow-edge period reported a longer effective high time -- the measurement "
                    & "is VIL-based, not VIH-based" severity error; errs := errs + 1; end if;
           if h_fast < to_unsigned(75, TICK_W) or h_fast > to_unsigned(90, TICK_W) then
               report "an 80-tick fully-high interval measured out of range" severity error;
               errs := errs + 1; end if;

           -- 6: stated directly: an 80-tick high phase reached by a 40-tick rise must measure about
           -- 80, not 120.
           scl_above_vil <= '1'; tick(20);
           scl_period(10, 100, 40, 80);
           fall_edge(10);
           tick(20);
           if h_log(n_hlog - 1) > to_unsigned(95, TICK_W) then
               report "the effective high time counted the transition" severity error;
               errs := errs + 1; end if;

           -- 7: an edge that never completes produces NO measurement. The line dips below VIH and
           -- comes back up without crossing VIL: that is noise on the high phase, not a falling
           -- edge, and timing it as one would report a fall that did not happen.
           nfall_before := n_fall;
           scl_above_vih <= '0'; tick(20);
           scl_above_vih <= '1'; tick(60);      -- back up without crossing VIL
           if n_fall /= nfall_before then
               report "an incomplete edge produced a fall measurement" severity error;
               errs := errs + 1; end if;

           -- 8: a STATIC bus measures nothing. No threshold crossings, no edges.
           viol_before := n_viol; nrise_before := n_rise;
           scl_above_vil <= '1'; scl_above_vih <= '1'; tick(400);
           if n_rise /= nrise_before or n_viol /= viol_before then
               report "a static bus produced edges or violations" severity error;
               errs := errs + 1; end if;

           if errs = 0 then
               report "i2c_edge_rate_monitor self-check complete: an edge rate needs two thresholds, "
                    & "tr and tf are separate maxima, the effective high time is VIH-based and "
                    & "excludes the transition, an incomplete edge is not an edge" severity note;
           else
               report "i2c_edge_rate_monitor self-check FAILED" severity error;
           end if;
           test_done <= '1';
           wait;
       end process;
   end architecture;

   $ iverilog -g2012 -o d7 i2c_edge_rate_monitor.sv i2c_edge_rate_monitor_tb.sv && ./d7
   PASS: an edge rate needs two thresholds, tr and tf are separate maxima, the effective high
   time is VIH-based and excludes the transition, an incomplete edge is not an edge
   i2c_edge_rate_monitor_tb.sv:250: $finish called at 34170000 (1ps)

   $ iverilog -g2005 -o v7 i2c_edge_rate_monitor.v i2c_edge_rate_monitor_tb.v && ./v7
   PASS: an edge rate needs two thresholds, tr and tf are separate maxima, the effective high
   time is VIH-based and excludes the transition, an incomplete edge is not an edge
   i2c_edge_rate_monitor_tb.v:263: $finish called at 34170000 (1ps)

   $ nvc -a i2c_edge_rate_monitor.vhd i2c_edge_rate_monitor_tb.vhd
   $ nvc -e i2c_edge_rate_monitor_tb && nvc -r i2c_edge_rate_monitor_tb --stop-time=700us
   ** Note: 34170ns+0: i2c_edge_rate_monitor self-check complete: an edge rate needs two
      thresholds, tr and tf are separate maxima, the effective high time is VIH-based and excludes
      the transition, an incomplete edge is not an edge

   // An edge is an interval, so the property needs both thresholds. An assertion written against
   // a single digital `sda` cannot express anything about tr at all -- the edge is precisely the
   // region where a single-threshold view has no value. This is the one place in the module
   // where the INTERFACE, not the property, is what makes the check possible.
   //
   //    sda_above_30  -- comparator at 0.3 VDD
   //    sda_above_70  -- comparator at 0.7 VDD

   int edge_ticks;
   always_ff @(posedge clk)
      if ($rose(sda_above_30) && !sda_above_70) edge_ticks <= 0;
      else                                      edge_ticks <= edge_ticks + 1;

   // tr as a MAXIMUM: bounded liveness, the shape Chapter 11.4 section 9 establishes. The
   // interesting failure is an edge that never completes, which no window-shaped property sees.
   property p_tr_max;
      @(posedge clk) ($rose(sda_above_30) && !sda_above_70) |-> ##[1:T_R_MAX] sda_above_70;
   endproperty
   assert property (p_tr_max)
      else $error("tr exceeded: 0.7 VDD not reached within %0d ticks of 0.3 VDD", T_R_MAX);

   // tr as a MINIMUM -- which section 6's monitor deliberately does NOT check, because it cannot
   // resolve 20 ns. In an environment whose sample clock CAN, this is the shape: a generate guard
   // so that a Standard-mode build, which has no rise-time minimum at all, does not carry a
   // vacuous assertion that a coverage report would score as passing.
   if (T_R_MIN > 0) begin : g_tr_min
      property p_tr_min;
         @(posedge clk) $rose(sda_above_70) |-> (edge_ticks >= T_R_MIN);
      endproperty
      assert property (p_tr_min)
         else $error("tr too FAST: %0d ticks, minimum %0d -- ringing risk", edge_ticks, T_R_MIN);
   end

   // The NEGATIVE property, and for this chapter it is about scope rather than polarity. tr and
   // tf are BOARD properties, so an assertion firing here does NOT indict the RTL -- and a
   // suite that treats it as an RTL failure will chase the wrong logic. The message says so.
   property p_edge_is_a_board_property;
      @(posedge clk) (viol_tr || viol_tf) |-> !rtl_fault_expected;
   endproperty
   assert property (p_edge_is_a_board_property)
      else $error("edge-rate violation: check Rp and Cb, NOT the state machine");

   // The unusual thing about this covergroup is that its axes are BOARD parameters. The design
   // space being covered is not the RTL's state space -- it is the set of boards the RTL might
   // be soldered onto, which is the space section 4's table lives in.
   covergroup i2c_edge_cg with function sample(int tr, int tf, int r_max, int r_min,
                                               int rp_ohms, int cb_pf, int vdd_mv, int mode);
      tr_margin: coverpoint (r_max - tr) {
         bins over       = {[$:-1]};
         bins exact      = {0};
         bins within_10  = {[1:10]};
         bins comfortable = {[11:$]};
      }

      // The too-FAST bin, which exists in no other covergroup in this module because no other
      // parameter has a minimum. A suite that only ever slows edges down has not tested it,
      // and section 5 says the failure it guards against is ringing misread as extra edges.
      tr_fast: coverpoint tr {
         bins too_fast = {[0:1]};
         bins near_min = {[2:5]};
         bins normal   = {[6:$]};
      }

      // Pull-up and capacitance as explicit axes, binned at section 4's boundaries. The
      // interesting bins are the ones the table above says are EMPTY -- a build that lands
      // there is a board error, and covering it proves the monitor reports it.
      pullup: coverpoint rp_ohms {
         bins too_strong = {[0:400]};      // below Rp(min) at most supplies: VOL not met
         bins typical    = {[401:2200]};
         bins too_weak   = {[2201:10000]}; // tr exceeded at any real Cb
      }
      cap: coverpoint cb_pf {
         bins light    = {[0:100]};
         bins moderate = {[101:250]};
         bins heavy    = {[251:400]};      // the resistive Fast-mode wall, section 4
         bins over_spec = {[401:$]};
      }

      // The cross that reproduces section 4's table. Cells corresponding to an EMPTY window
      // must show a violation, and a run that reports none of them has not exercised the
      // region where the specification's own numbers do not close.
      rp_x_cap: cross pullup, cap;

      // And speed mode, because which constraint BINDS flips with it -- Cb in Standard-mode,
      // the resistor in Fast-mode and Fm+. Same reasoning as Chapter 11.5's speed cross.
      speed: coverpoint mode { bins standard = {0}; bins fast = {1}; bins fm_plus = {2}; }
      tr_x_speed: cross tr_margin, speed;
   endgroup