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Verilog · Chapter 12.2.3 · Switch-Level Modeling

Transmission Gates in Verilog — Passing Both Logic Values Cleanly

A transmission gate fixes the degradation problem of single-transistor pass logic: one NMOS passes a weak 1 and one PMOS passes a weak 0, so neither alone carries both logic values cleanly. Wire them in parallel with complementary controls and the structure passes a strong 0 through the NMOS and a strong 1 through the PMOS, so any value goes through at full strength. The transmission gate is bidirectional, meaning a signal flows either way, and controlled, meaning it connects or isolates on an enable. It is the building block of transmission-gate multiplexers, latches, and switch networks in custom CMOS. This page shows the gate as an nmos and pmos pair, the cmos primitive, and the tranif bidirectional switch, plus the structures they build.

Foundation12 min readVerilogTransmission GateSwitch-LevelPass Transistorcmos

Chapter 12 · Section 12.2.3 · Switch-Level Modeling

1. The Engineering Problem

Single-transistor pass logic degrades one value (12.2.1) — an NMOS weakens a 1, a PMOS weakens a 0 — so a switch that must carry both logic values cleanly needs more than one transistor:

A transmission gate is an NMOS and a PMOS in parallel with complementary controls: the NMOS passes a strong 0, the PMOS passes a strong 1, so both logic values go through at full strength. It is bidirectional and controlled.

This page builds the transmission gate and the muxes and latches it enables.

2. Mental Model — Two Transistors in Parallel Cover Both Values

3. Building a Transmission Gate

Three equivalent ways to express it:

transmission-gate.v
Azvya Education Pvt. Ltd.VLSI Mentor
Snippet
   // 1. NMOS + PMOS in parallel (complementary controls):
   nmos (out, in,  en);       // passes strong 0 when en=1
   pmos (out, in, ~en);       // passes strong 1 when en=1 (pmos on at gate 0)
 
   // 2. the cmos primitive (NMOS+PMOS combined):
   cmos (out, in, en, ~en);   // cmos (out, data, ncontrol, pcontrol)
 
   // 3. the bidirectional tranif switch:
   tranif1 (out, in, en);     // connect when en=1, isolate when en=0

All three are a controlled, full-strength, bidirectional pass connection between in and out, enabled by en. The nmos+pmos form makes the complementary structure explicit; cmos packages it; tranif1 is the bidirectional-switch shorthand. (Note tranif1 is purely bidirectional; the nmos+pmos and cmos forms drive out from in but pass full strength.)

Visual A — the transmission gate

Transmission gate structureinsourcenmos (en)passes strong 0pmos (~en)passes strong 1outfull-strength,bidirectional12
A transmission gate is an NMOS and a PMOS in parallel with complementary controls. When enabled, the NMOS passes the strong 0 and the PMOS the strong 1, so any value passes at full strength (unlike a lone transistor, which degrades one value). When disabled, both are off and the two sides are isolated. It is bidirectional — signals flow either way.

4. What Transmission Gates Build

  • Transmission-gate mux — one transmission gate per input, complementary enables, exactly one enabled at a time. Each input passes at full strength (unlike the degrading NMOS-only mux of 12.2.1).
  • Transmission-gate latch — a transmission gate feeding a storage node, with feedback, gives a level-sensitive latch — a common custom-CMOS storage structure.
  • Switch networks — bidirectional routing fabrics where signals pass through enabled transmission gates.
tx-gate-mux.v
Azvya Education Pvt. Ltd.VLSI Mentor
Snippet
   // 2:1 transmission-gate mux — full-strength selection
   nmos (y, in0, ~sel);  pmos (y, in0,  sel);   // in0 leg (enabled when sel=0)
   nmos (y, in1,  sel);  pmos (y, in1, ~sel);   // in1 leg (enabled when sel=1)

Each leg is a transmission gate; complementary sel enables exactly one. Both inputs reach y at full strength — the clean version of the pass-transistor mux.

5. Common Mistakes

  1. Using a lone NMOS/PMOS where both values pass — degrades one value; use a transmission gate (§1, 12.2.1).
  2. Non-complementary controls — the NMOS and PMOS must be enabled together (en / ~en); same-polarity controls break it (§3).
  3. Both legs enabled in a tx-gate mux — two inputs drive the output and contend; enables must be one-at-a-time (§4).
  4. Forgetting bidirectionality — a transmission gate passes either way; in some uses the drive direction matters (§2).

6. Debugging Lab

One transmission-gate debug post-mortem

7. Interview Q&A

8. Exercises

Exercise 1 — Why both transistors?

Explain why a transmission gate needs both an NMOS and a PMOS to pass both logic values cleanly.

Exercise 2 — Three forms

Write a transmission gate enabled by g three ways: (a) nmos+pmos; (b) cmos; (c) tranif1.

Exercise 3 — Fix the controls

A transmission gate uses en on both transistors and degrades values. Give the fix.

9. Summary

A transmission gate passes both logic values at full strength:

  • NMOS ∥ PMOS, complementary controls — NMOS passes the strong 0, PMOS the strong 1; together, a clean full-strength two-way switch.
  • Three forms — explicit nmos+pmos, the cmos primitive, or bidirectional tranif1.
  • Builds transmission-gate muxes (full-strength selection), latches, and switch networks.
  • The fix for single-transistor pass degradation (12.2.1).

The last 12.2 sub-topic covers strength-reducing switches: Chapter 12.2.4 Resistive MOS Switches drills the rnmos/rpmos/rcmos/rtran variants that lower the strength of the passed signal.