PMOS & NMOS Behavior in Verilog — Unidirectional Switch Primitives

Chapter 12 · Section 12.2.1 · Switch-Level Modeling

1. The Engineering Problem

The nmos and pmos primitives are the workhorses of switch-level modeling, but using them correctly requires holding two facts at once: when each conducts, and what strength it passes. Get the first wrong and the switch is on at the wrong time; ignore the second and you build pass logic that silently degrades a logic value.

nmos conducts at gate 1 (strong 0, weak 1); pmos conducts at gate 0 (strong 1, weak 0). Pass-transistor logic must account for both the control polarity and the strength asymmetry.

This page drills the two primitives and the pass-transistor structures they build.

2. Mental Model — Two Complementary Pass Switches

3. Instantiation and Conduction

   nmos (out, data, gate);    // out = data when gate=1, else z; strong 0 / weak 1
   pmos (out, data, gate);    // out = data when gate=0, else z; strong 1 / weak 0

   // optional instance name and strength:
   nmos g1 (out, data, gate);

Terminal order is (output, data, control) — the output first, then the data being passed, then the gate control. When off, the output is high-impedance (z), so the downstream node floats unless another driver holds it.

4. Pass-Transistor Logic

A pass transistor routes a signal under control — a switch on a data path:

   // route 'a' to 'y' when 'en' is high (NMOS pass switch)
   nmos (y, a, en);

   // a 2:1 pass-transistor mux (two NMOS, complementary enables):
   nmos (y, in0, ~sel);       // in0 when sel=0
   nmos (y, in1,  sel);       // in1 when sel=1

The mux uses two NMOS switches with complementary enables so exactly one passes at a time. It works — but if in0/in1 can be 1, the passed high is weak (NMOS degrades 1s, §3), which is the pitfall §5 addresses. Pass-transistor logic is compact but must respect the strength asymmetry.

Visual A — NMOS and PMOS pass switches

5. The Degradation Pitfall

A single NMOS passing a logic 1 gives a weak 1; a single PMOS passing a 0 gives a weak 0. The weak value may be misread downstream or lose a strength contest. The standard fix is a transmission gate (NMOS + PMOS in parallel, 12.2.3), which passes both values at full strength — the NMOS handles the 0, the PMOS handles the 1. Single-transistor pass logic is used only where one logic value is passed, or where the degradation is acceptable and later restored by a gate.

6. Common Mistakes

1. Passing a 1 through a lone NMOS (or a 0 through a lone PMOS) — degraded value; use a transmission gate (§5).
2. Wrong control polarity — NMOS at gate 1, PMOS at gate 0 (§3).
3. Wrong terminal order — (output, data, control) (§3).
4. Floating output when off — the off state is z; another driver must hold the node.

7. Debugging Lab

// 2:1 mux from NMOS pass transistors. Inputs can be 0 or 1.
nmos (y, in0, ~sel);
nmos (y, in1,  sel);

// When the selected input is 1, the NMOS passes a WEAK 1 to 'y'. Downstream
// gates may misread it, and on a shared node it can lose to another driver.
// 0s pass fine (strong); only the high is degraded.

// Transmission-gate mux legs: each leg is an nmos+pmos pair.
nmos (y, in0, ~sel);  pmos (y, in0,  sel);   // leg 0 passes both values
nmos (y, in1,  sel);  pmos (y, in1, ~sel);   // leg 1 passes both values

// Now each selected input reaches 'y' at full strength for both 0 and 1.

8. Interview Q&A

9. Exercises

Exercise 1 — Conduction and strength

For nmos (y, d, g) and pmos (y, d, g), state when each conducts and the strength of the passed 0 and 1.

Exercise 2 — Build a pass switch

Write a switch that passes data to out only when en is 1, and state what out is when en is 0.

Exercise 3 — Fix the degradation

A lone NMOS passes a control signal that is sometimes 1, and the 1 is weak. Give the fix.

10. Summary

The unidirectional MOS switch primitives:

• nmos — conducts at gate 1; strong 0, weak 1; good 0-passer/pull-down.
• pmos — conducts at gate 0; strong 1, weak 0; good 1-passer/pull-up.
• Order (output, data, control); off → z.
• Pass-transistor logic routes signals but degrades one value per transistor type — pair them (transmission gate) to pass both cleanly.

The next sub-topic builds gates from these: Chapter 12.2.2 CMOS Logic Gates assembles inverters, NAND, and NOR from complementary NMOS pull-down and PMOS pull-up networks.

Related Tutorials

• Switch Level Primitives — Chapter 12.2; the parent primitive survey.
• Understanding MOS Behaviour — Chapter 12.1; the device behaviour applied here.
• Transmission Gates — Chapter 12.2.3; the both-values pass fix for degradation.
• Signal Strengths — Chapter 5.1.2; the strength system behind the asymmetry.