Resistive MOS Switches in Verilog — rnmos, rpmos, rcmos & rtran

Chapter 12 · Section 12.2.4 · Switch-Level Modeling

1. The Engineering Problem

Some switch-level circuits need a device that passes a signal but weakens it — a high-resistance transistor whose output should lose to a stronger driver on a shared node. Verilog provides resistive switch primitives for exactly this:

The resistive switches (rnmos, rpmos, rcmos, rtran*) behave like their counterparts but reduce the strength of the passed signal by one level. Their output therefore loses, in resolution, to a non-resistive driver of the original strength.

This short page drills the resistive variants and the strength reduction they apply.

2. Mental Model — Same Switch, Lower Strength

3. The Resistive Variants

   rnmos (out, data, gate);    // like nmos, output strength reduced
   rpmos (out, data, gate);    // like pmos, output strength reduced
   rcmos (out, data, ng, pg);  // like cmos, output strength reduced

   rtran    (a, b);            // like tran, strength reduced
   rtranif1 (a, b, ctrl);      // like tranif1, strength reduced
   rtranif0 (a, b, ctrl);      // like tranif0, strength reduced

Same syntax, same conduction, same direction as the non-resistive forms — only the passed strength is lowered. A strong 1 through an nmos stays strong (subject to the NMOS weak-1 caveat); through an rnmos it is reduced to a pull (or lower) strength.

4. Strength Reduction in Resolution

The point of a resistive switch is that its output loses to a stronger driver. On a node driven by both a resistive and a non-resistive switch carrying different values, the non-resistive (stronger) one wins; carrying the same value, the result takes the stronger strength. This is how ratioed circuits work — a weak (resistive) pull-up or keeper holds a node, but a strong driver overrides it. The full resolution mechanics are 12.3; here the takeaway is that resistive = weaker = loses.

Visual A — resistive reduces strength

5. Common Mistakes

1. Expecting a resistive switch to pass full strength — it reduces strength by one level (§2/§3).
2. Using a resistive switch where a strong driver is needed — its output loses to non-resistive drivers (§4).
3. Confusing resistive with non-resistive in resolution — the strength difference decides the node (§4, 12.3).

6. Interview Q&A

7. Exercises

Exercise 1 — Strength reduction

A strong 1 is passed through an rnmos. What strength does the output have (one level lower on the strength scale)?

Exercise 2 — Who wins?

A node is driven by an nmos passing a 0 and an rpmos passing a 1. Which value wins, and why?

Exercise 3 — Choose the primitive

You need a weak keeper that holds a node but is overridden by any strong driver. Which kind of switch (resistive or non-resistive) fits, and why?

8. Summary

The resistive switch primitives behave like their counterparts but reduce signal strength:

• rnmos / rpmos / rcmos / rtran* — same conduction and direction as the non-resistive forms, but the passed signal is one strength level weaker.
• In resolution, resistive loses — a resistive output is weaker than a non-resistive one, so the non-resistive driver wins; this models ratioed and charge-sharing circuits.

This completes the 12.2 switch primitives. The chapter now turns to the mechanism that decides node values: Chapter 12.3 Drive Strength and Resolution explains how the strengths of multiple drivers combine to determine the value on a switch-level node — the heart of switch-level simulation.

Related Tutorials

• Switch Level Primitives — Chapter 12.2; the non-resistive counterparts.
• Signal Strengths — Chapter 5.1.2; the strength scale these switches reduce on.
• Transmission Gates — Chapter 12.2.3; the full-strength pass structure (contrast).
• Drive Strength and Resolution — Chapter 12.3; how strengths combine to decide a node.