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Verilog · Chapter 12.1 · Switch-Level Modeling

Understanding MOS Behaviour in Verilog — Transistors as Switches

Before the switch-level primitives make sense, you need the device behind them, a MOS transistor acting as a switch. An NMOS transistor conducts, connecting its source and drain, when its gate is driven high, while a PMOS conducts when its gate is driven low. When off, each presents a high-impedance open circuit. The subtlety that makes the switch level interesting is signal degradation. An NMOS passes a strong 0 but only a weak 1, and a PMOS passes a strong 1 but only a weak 0. That strong and weak asymmetry is exactly why CMOS pairs them, since the NMOS pulls a node firmly to 0, the PMOS pulls it firmly to 1, and together they drive a full-strength output. This page explains MOS switching, the off state, and strength degradation as the foundation for the primitives and CMOS circuits that follow.

Foundation14 min readVerilogMOSNMOSPMOSCMOSSwitch-Level

Chapter 12 · Section 12.1 · Switch-Level Modeling

1. The Engineering Problem

The switch-level primitives (nmos, pmos, cmos) only make sense once you understand the device they model — a transistor used as a switch. And the single fact that makes switch-level circuits work is not obvious:

An NMOS transistor passes a strong 0 but a weak 1; a PMOS passes a strong 1 but a weak 0. This strong/weak asymmetry is why CMOS pairs them — NMOS to pull down, PMOS to pull up.

If you treat both transistors as ideal switches that pass any value perfectly, you cannot explain why a CMOS gate uses complementary devices, why a single NMOS pass-transistor degrades a logic 1, or how drive-strength resolution decides a node. This page builds that foundation: how a MOS transistor switches, its high-impedance off state, and the strength degradation that drives CMOS design.

2. Mental Model — A Transistor Is a Gate-Controlled Switch

Visual A — NMOS and PMOS conduction

NMOS and PMOS conduction and strengthNMOSon at gate=1strong 0, weak 1pulls down wellPMOSon at gate=0strong 1, weak 0pulls up well12
An NMOS conducts (connects source to drain) when its gate is 1, and is high-impedance when its gate is 0 — and it passes a strong 0 but a weak 1. A PMOS is the complement: it conducts when its gate is 0, is high-impedance when its gate is 1, and passes a strong 1 but a weak 0. The opposite control and opposite strong-value are why CMOS pairs them.

3. NMOS Behaviour

An NMOS transistor, modeled as a switch:

  • Gate = 1 → conducts. The source-to-drain connection is on; the value at the source appears at the drain.
  • Gate = 0 → off (high-impedance). The connection is open; the drain is not driven by this transistor.
  • Strength: strong 0, weak 1. An NMOS passes a 0 at full strength but a 1 is degraded (it cannot pull all the way to a strong 1). So an NMOS is a good pull-down but a poor pull-up.

This is why an NMOS pass-transistor that tries to pass a logic 1 produces a degraded (weak) high — a classic switch-level effect, and a reason single-NMOS pass logic is avoided for driving 1s.

4. PMOS Behaviour

A PMOS transistor is the complement of the NMOS:

  • Gate = 0 → conducts. (Opposite control to NMOS — PMOS turns on with a low gate.)
  • Gate = 1 → off (high-impedance).
  • Strength: strong 1, weak 0. A PMOS passes a 1 at full strength but a 0 is degraded. So a PMOS is a good pull-up but a poor pull-down.

The PMOS is the mirror image: it drives 1s firmly and 0s weakly, controlled by a low gate. The two devices are complementary in both their control polarity and their strong direction.

5. Why CMOS Pairs Them

Put the two facts together and CMOS design follows directly:

  • An NMOS network (transistors that conduct on high inputs) connects the output to ground to drive a strong 0.
  • A PMOS network (transistors that conduct on low inputs) connects the output to power to drive a strong 1.
  • For any input, exactly one network conducts, so the output is driven full-strength to the correct value — strong 0 from the NMOS pull-down, strong 1 from the PMOS pull-up.

This is the CMOS inverter (12.4): a PMOS from power to output and an NMOS from output to ground, both gated by the input. When the input is 0, the PMOS conducts and drives a strong 1; when the input is 1, the NMOS conducts and drives a strong 0. The complementary pairing gives a clean, full-strength output in both directions — which a single transistor type, with its weak direction, cannot.

Visual B — CMOS uses both for full-strength output

CMOS pairs NMOS and PMOS for full strength

data flow
CMOS pairs NMOS and PMOS for full strengthinputdrives both gatesPMOS network →powerdrives strong 1NMOS network →grounddrives strong 0full-strengthoutputstrong 0 and strong 1
A CMOS gate uses a PMOS network to drive the output to a strong 1 (from power) and a complementary NMOS network to drive it to a strong 0 (from ground). For any input exactly one network conducts, so the output is full-strength in both directions — which a single transistor type could not achieve because of its weak direction.

6. Industry Perspective

  • Strength degradation is why pass-transistor logic is careful. A single NMOS pass-transistor degrades a logic 1, so transmission gates (NMOS + PMOS in parallel, 12.2) are used to pass both values cleanly — a direct consequence of the strong/weak asymmetry.
  • CMOS is the universal logic family because of complementary strength. The full-strength output in both directions, with no static current, is what made CMOS dominate — and it is exactly the NMOS-pull-down / PMOS-pull-up behaviour this page describes.
  • Switch-level simulation models strength. Verilog's strength system (5.1.2) captures strong/weak passing so switch-level simulation reflects which transistor wins on a shared node.
  • This is device intuition, not RTL. Understanding MOS switching helps you read transistor-level cells and pass-transistor structures; you design above it, in RTL.

7. Common Mistakes

  1. Treating NMOS and PMOS as ideal (lossless) switches — they degrade one logic value each (§3/§4).
  2. Using a single NMOS to pass a logic 1 — it produces a weak 1; use a transmission gate (§5, 12.2).
  3. Confusing the control polarity — NMOS conducts at gate 1, PMOS at gate 0 (§2).
  4. Forgetting the off state is high-impedance — a non-conducting transistor floats its node (§2).
  5. Ignoring strength — switch-level node values are decided by strength resolution (12.3).

8. Debugging Lab

Two MOS-behaviour debug post-mortems

Pitfall 1 — single NMOS pass-transistor degrades a logic 1
Buggy Code
// A single NMOS used to pass a signal (intended as a switch for both 0 and 1):
nmos (out, data, en);          // out = data when en=1

// When 'data' is 1, the NMOS passes a WEAK (degraded) 1 to 'out', not a
// strong 1. Downstream logic may misread the weak high, or it loses a
// strength contest against another driver. The 0 passes fine (strong).
Symptom

A pass-transistor switch works correctly when passing 0 but produces a weak or unreliable high when passing 1 — downstream gates sometimes misread it, or it loses to another driver on a shared node.

Root Cause

An NMOS passes a strong 0 but only a WEAK 1 (strength degradation). Using a single NMOS as a pass-transistor for both logic values means the 1 it passes is degraded — fine for pulling a node down, unreliable for driving it up. This is the fundamental NMOS asymmetry: good pull-down, poor pull-up.

The fix is a TRANSMISSION GATE — an NMOS and PMOS in parallel — which passes both 0 (via the NMOS) and 1 (via the PMOS) at full strength.

Fix
// Transmission gate: NMOS + PMOS in parallel, complementary controls.
nmos (out, data,  en);         // passes strong 0
pmos (out, data, nen);         // passes strong 1   (nen = ~en)

// Together they pass both logic values at full strength — the standard
// pass-gate structure (drilled in 12.2). Don't pass a 1 through a lone NMOS.
Pitfall 2 — wrong transistor control polarity
Buggy Code
// Intent: a PMOS pull-up that conducts to drive the output to 1 when the
// input 'a' is high. But PMOS conducts on a LOW gate.
supply1 vdd;
pmos (y, vdd, a);              // conducts when a=0, NOT when a=1

// The designer expected the pull-up to turn on when a=1, but PMOS turns on
// when its gate is 0. So the pull-up is active for the wrong input value.
Symptom

A PMOS pull-up drives the output high for the wrong input value — it conducts when the input is low, not high, opposite to what the designer intended.

Root Cause

Control polarity. A PMOS conducts when its gate is 0 (low), the OPPOSITE of an NMOS (which conducts when its gate is 1). The designer treated the PMOS like an NMOS, expecting it to turn on with a high gate. In a CMOS inverter this is exactly right — the PMOS pull-up conducts when the input is 0, driving the output to 1 — but if the intent was 'pull up when a=1', the polarity is wrong.

The fix depends on intent: for a CMOS inverter the polarity is correct (PMOS pulls up when input is 0); if the input must be inverted first, drive the PMOS gate with ~a, or rethink the structure.

Fix
// For a CMOS inverter (output = ~a), the PMOS pull-up correctly conducts
// when a=0, paired with an NMOS pull-down conducting when a=1:
supply1 vdd;  supply0 gnd;
pmos (y, vdd, a);             // a=0 → y driven to strong 1
nmos (y, gnd, a);             // a=1 → y driven to strong 0
// This IS an inverter. PMOS-on-low / NMOS-on-high is the CMOS convention.

9. Interview Q&A

10. Exercises

Exercise 1 — Conduction conditions

State when each conducts and what it is otherwise: (a) an NMOS with gate = 1; (b) an NMOS with gate = 0; (c) a PMOS with gate = 1; (d) a PMOS with gate = 0.

Exercise 2 — Strength of passed values

For each, state the strength of the passed value: (a) NMOS passing a 0; (b) NMOS passing a 1; (c) PMOS passing a 1; (d) PMOS passing a 0.

Exercise 3 — Reason about CMOS

(a) Why does a CMOS inverter use a PMOS pull-up and an NMOS pull-down rather than two of the same type? (b) For a CMOS inverter, which transistor conducts when the input is 0, and what value does the output get?

Exercise 4 — Fix the pass logic

A single NMOS is used to pass a control signal that can be 0 or 1, and the 1 comes through weak. Explain why, and give the standard fix.

11. Summary

A MOS transistor in switch-level modeling is a gate-controlled switch with a strength asymmetry:

  • NMOS conducts at gate 1 (off = high-impedance); passes a strong 0, weak 1 — a good pull-down.
  • PMOS conducts at gate 0 (off = high-impedance); passes a strong 1, weak 0 — a good pull-up.
  • Off is high-impedance — a non-conducting transistor floats its node.

The consequence:

  • CMOS pairs them — NMOS network to drive a strong 0, PMOS network to drive a strong 1 — for a full-strength output in both directions.
  • Single-transistor pass logic degrades one value — pass a 1 through a lone NMOS and it comes through weak; use a transmission gate.

The discipline this page instils:

  • Remember the polarity — NMOS on at 1, PMOS on at 0.
  • Remember the strong direction — NMOS strong 0, PMOS strong 1.
  • Pair them for full strength — the basis of CMOS and transmission gates.

The next page drills the constructs that model these devices: Chapter 12.2 Switch Level Primitives covers the MOS switch primitives — nmos, pmos, cmos, the bidirectional tran family, and the pullup/pulldown sources — with their syntax and the structures they build.