User-Defined Primitives (UDPs) in Verilog — Chapter 16 Overview

Chapter 16 · User-Defined Primitives (Overview)

1. The Engineering Problem

The built-in gate primitives (Chapter 11) cover the standard logic gates — but modeling a custom primitive (an ASIC standard cell's exact behaviour, including its handling of unknowns) sometimes calls for defining a primitive by its truth table directly. The question:

How do you define a custom primitive by its truth table — like the built-in gates but with your own behaviour — and when does that matter?

The answer is the user-defined primitive (UDP): a single-output primitive whose behaviour is given by a table. It is reference material — not synthesizable, not for RTL design — used to model library cells and legacy gate-level behaviour compactly.

2. Mental Model — A Custom Primitive Defined by a Truth Table

3. The Two Kinds of UDP

   // COMBINATIONAL UDP — output is a function of inputs (a truth table):
   primitive mux_udp (out, a, b, sel);
       output out;
       input  a, b, sel;
       table
           // a b sel : out
              1 ? 0   : 1;     // sel=0 → out = a
              0 ? 0   : 0;
              ? 1 1   : 1;     // sel=1 → out = b
              ? 0 1   : 0;
       endtable
   endprimitive
 
   // SEQUENTIAL UDP — output depends on state + input transitions (a latch):
   primitive latch_udp (q, d, en);
       output q;  reg q;       // 'reg' → sequential (stateful)
       input  d, en;
       table
           // d en : q(state) : q(next)
              ? 0  :    ?      :   -;     // en=0 → hold (no change)
              0 1  :    ?      :   0;     // en=1 → q = d
              1 1  :    ?      :   1;
       endtable
   endprimitive

• Combinational UDP — the table maps inputs to the output; ? is a don't-care. (Drilled in 16.1.)
• Sequential UDP — the output is declared reg (stateful), and the table includes the current state and next state; - means "no change" (hold). (Drilled in 16.2.)

4. Why UDPs Are Reference, Not Design

The context that frames this chapter:

• Not synthesizable — synthesis does not produce or accept UDPs as design logic; they are simulation models.
• Cell-library modeling — a UDP can model an ASIC standard cell's exact behaviour (including precise unknown/x handling) more compactly than a gate network — their main real use.
• Legacy gate-level — older gate-level models and some primitive libraries use UDPs.
• You read, you don't author — new design is RTL; UDPs are encountered in cell libraries and legacy code, which is why this chapter is reference.

5. What This Chapter Covers

6. Common Misconceptions

"UDPs are how you write custom logic in RTL." False. UDPs are not synthesizable and not for RTL design — they are simulation models for cells. Custom logic in RTL is written behaviourally (Chapter 14).

"A UDP can have multiple outputs." False. A UDP has exactly one output (the first port). For multiple outputs, use a module.

"UDPs are common in modern design." Misleading. They are legacy/reference — used mainly in cell-library modeling. Most engineers read them (in libraries) rather than write them.

7. Summary

A user-defined primitive (UDP) is a custom single-output primitive defined by a truth table:

• Single output (first port), defined with primitive/endprimitive and a table/endtable.
• Two kinds — combinational (truth table of inputs → output) and sequential (output depends on state + input transitions; output is reg).
• Reference — not synthesizable; used for cell-library modeling and legacy gate-level.

The sub-topics drill each: Chapter 16.1 Combinational UDPs, 16.2 Sequential UDPs, and 16.3 UDPs Advanced Techniques. After UDPs, the remaining chapters cover delay and timing reference topics (17–19).

Related Tutorials

• Pre-defined Gate Primitives — Chapter 11.1; the built-in primitives UDPs extend.
• Gate-Level Modeling — Chapter 11; the structural level UDPs belong to.
• reg — Chapter 5.2.1; the reg that makes a sequential UDP stateful.
• Behavioural Modeling — Chapter 14; how custom logic is actually written for design.