Switch-Level Modeling in Verilog — Chapter 12 Overview

Chapter 12 · Switch-Level Modeling (Overview)

1. The Engineering Problem

Below the gate is the transistor. Some circuits — pass-transistor multiplexers, transmission-gate latches, custom CMOS cells, switch networks — are most naturally described not as logic gates but as MOS switches wired between power, ground, and signal nodes. The question this specialized chapter answers:

How does Verilog model a circuit at the transistor level — as MOS switches that connect or disconnect nodes — and when does that matter, given that digital RTL is written far above this level?

The answer is switch-level modeling: MOS switch primitives (nmos, pmos, cmos, tran, …) that act as controlled connections, with the result on each node decided by Verilog's drive-strength resolution. This is reference material — modern digital design is synthesized from RTL, not modeled transistor-by-transistor — but it explains pass-transistor logic, CMOS cell behaviour, and how strength resolution works, which is occasionally exactly what you need.

2. What Is Switch-Level Modeling?

Switch-level modeling describes a circuit as transistors used as switches — each MOS device either connects two nodes (passing a value) or disconnects them (high-impedance), under control of its gate:

   // A CMOS inverter at the switch level — a PMOS pull-up and NMOS pull-down:
   supply1 vdd;
   supply0 gnd;
   pmos (y, vdd, a);        // pull y to 1 (vdd) when a = 0
   nmos (y, gnd, a);        // pull y to 0 (gnd) when a = 1

This is the same inverter that gate-level writes as `not (y, a);` and dataflow as `assign y = ~a;` — but spelled out as two transistors connecting y to power or ground depending on the input. The switch-level form is the transistor schematic in text, the lowest possible description, and far below where digital design is normally written.

3. Mental Model — Transistors as Controlled Switches, Resolved by Strength

Visual A — switch-level is the lowest abstraction

4. The Switch Primitives

Verilog provides built-in MOS switch primitives (drilled in 12.2):

   nmos (out, data, gate);      // out = data when gate=1, else z
   pmos (out, data, gate);      // out = data when gate=0, else z
   cmos (out, data, ng, pg);    // combined NMOS/PMOS switch
   tranif1 (a, b, ctrl);        // bidirectional connection when ctrl=1
   pullup  (net);               // weak 1 source on 'net'

These build CMOS gates, transmission-gate muxes/latches, and pass-transistor networks at the transistor level. The chapter drills each, with the drive-strength resolution that decides node values.

5. When Switch-Level Modeling Is Used

Reference-appropriate context — the narrow places switch-level appears:

• Pass-transistor and transmission-gate logic — muxes, XOR cells, and latches built from transmission gates are naturally switch-level.
• Custom CMOS cell modeling — modeling a standard cell or a custom gate at the transistor level (e.g. for a library or a specialized circuit).
• Switch networks and analog-adjacent circuits — charge-sharing, dynamic logic, and circuits where strength and connectivity matter more than boolean function.
• Teaching CMOS structure — switch-level shows how a CMOS gate is built from complementary transistors, which is pedagogically useful.

You do not model synthesizable digital logic at the switch level — it is far too low and is rejected by synthesis (the foundations chapters noted these constructs are a fraction of a percent of real RTL). This chapter equips you to understand the transistor level, not to design there.

6. What This Chapter Covers

7. Common Misconceptions

"Switch-level is how you design digital circuits." False. Digital design is written in dataflow/behavioural RTL and synthesized to standard cells. Switch-level is the transistor view — reference for specialized cases, not authoring.

"Switch primitives synthesize." False. MOS switch primitives are not synthesizable to a standard-cell flow; they model transistor structure for simulation, not RTL for synthesis.

"You can ignore drive strength at the switch level." Misleading. Switch-level modeling is fundamentally about strength — which transistor wins on a shared node is a strength-resolution question (Chapter 5.1.2). Strength is the core of this chapter, not a detail.

8. Summary

Switch-level (transistor) modeling describes a circuit as MOS switches — nmos, pmos, cmos, bidirectional tran, and pullup/pulldown sources — the lowest Verilog abstraction, below gate-level.

The core ideas:

• MOS primitives are controlled switches — NMOS conducts at 1, PMOS at 0; they connect or disconnect (high-impedance) nodes.
• Node values are decided by drive-strength resolution (Chapter 5.1.2) — switch-level is fundamentally about strength.
• It is reference, not authoring — pass-transistor logic, custom cells, and switch networks, not synthesizable digital design.

The first sub-page builds the foundation: Chapter 12.1 Understanding MOS Behaviour explains how a MOS transistor acts as a switch — NMOS and PMOS conduction, and the strong/weak signal degradation that makes CMOS pair them. The chapter then drills the primitives (12.2), strength resolution (12.3), and practical CMOS circuits (12.4–12.5). After this reference chapter, the RTL core resumes at the level you design in: behavioural modeling (Chapter 14).

Related Tutorials

• Gate-Level Modeling — Chapter 11; the logic-gate level just above switch-level.
• Signal Strengths — Chapter 5.1.2; the drive-strength system that resolves switch-level nodes.
• supply0 and supply1 — Chapter 5.1.6; the power/ground nets switch-level circuits connect to.
• wire and tri Nets — Chapter 5.1.1; the nets and high-impedance state switches produce.