Switch-Level Advanced Examples in Verilog — Full Adder, Dynamic Logic & Limits

Chapter 12 · Section 12.5 · Switch-Level Modeling

1. The Engineering Problem

The building blocks of 12.1–12.4 scale to complete transistor-level circuits — arithmetic cells, dynamic logic, custom structures. Seeing a few larger examples consolidates the switch level; recognizing their limit closes the chapter:

Switch-level modeling scales to full circuits (a CMOS full adder, dynamic logic), but even these are reference: digital systems are designed at the register-transfer level and synthesized to cells, not modeled transistor-by-transistor.

This page sketches two advanced structures and the boundary that ends the gate/switch-level reference arc.

2. A CMOS Full Adder

A full adder (sum, cout from a, b, cin) is a classic compound-gate CMOS circuit. The logic:

• `cout = (a & b) | (cin & (a ^ b))` — a majority function, efficiently a single AOI-style complementary stage.
• `sum = a ^ b ^ cin` — XOR of the three, often built from transmission gates or a compact CMOS XOR.

// Switch-level full adder — sketch (carry as a compound CMOS gate)
module cmos_full_adder (input a, b, cin, output sum, cout);
    supply1 vdd;  supply0 gnd;
    // carry: cout = majority(a, b, cin) — a complementary network
    // (NMOS pull-down realizes the inverse-carry condition; PMOS the dual)
    // ... AOI-style PDN/PUN for the majority function ...
 
    // sum: a ^ b ^ cin — transmission-gate XOR network
    // ... TG-based XOR using a^b then ^cin ...
endmodule

The "mirror adder" arranges the carry's pull-down and pull-up networks symmetrically to share transistors, and the sum reuses the carry's internal nodes — a dense, fast cell. The point here is recognition: a full adder at the transistor level is complementary networks (for carry) plus transmission-gate XORs (for sum), built from exactly the primitives of this chapter. (You would write `assign {cout, sum} = a + b + cin;` in RTL, 13.2, and let synthesis pick an adder cell.)

Visual A — CMOS full adder structure

3. Dynamic Logic

Static CMOS uses complementary PUN/PDN that always drive the output. Dynamic logic trades that robustness for speed and density using a clock:

• Precharge phase (clock low): a PMOS precharges the output node to 1.
• Evaluate phase (clock high): an NMOS pull-down network conditionally discharges the node based on the inputs; a foot NMOS gated by the clock enables evaluation.

// Dynamic gate sketch — precharge then evaluate
//   clk=0: pmos precharges 'out' to 1
//   clk=1: nmos pull-down network (inputs) conditionally discharges 'out'
//   the output is VALID only during evaluate; it holds charge otherwise

Dynamic logic uses only an NMOS pull-down network (no PMOS logic network), so it is smaller and faster — but the output is a dynamically held charge that is valid only during evaluate and must be refreshed (it leaks). It relies on charge storage and timing, which is exactly why the switch-level strength and high-impedance concepts (12.3, charge-storage strengths) matter. Dynamic logic is used in high-speed custom circuits and is a clear illustration of why charge and strength are switch-level concerns.

4. The Limits of Switch-Level Modeling

These advanced examples reinforce the chapter's framing: switch-level is powerful for modeling transistor structure, but it is reference, not design:

• It does not synthesize to a standard-cell flow. Switch-level primitives model transistors for simulation; you cannot write a chip's functional logic this way for synthesis.
• It is verbose and low-level. A full adder is a one-line + in RTL versus a transistor network at the switch level.
• It is for narrow uses — custom cells, pass-transistor and dynamic circuits, switch networks, and understanding standard cells — not for building digital systems.

The boundary that closes the reference arc:

You read circuits at the gate and switch levels (netlists, cells, custom blocks); you design at the register-transfer level in dataflow and behavioural RTL, and synthesis maps it down to these cells.

5. Industry Perspective

• Custom-cell and full-custom design uses switch-level. Datapath cells, memory bit-cells, and high-speed dynamic logic are designed and modeled at the transistor level — the narrow domain where this chapter's content is authored, not just read.
• Standard-cell digital design does not. The vast majority of chips are RTL synthesized to a cell library; engineers read switch/gate level (cells, netlists) but design above it.
• Dynamic logic is specialized. Domino and other dynamic styles appear in high-performance custom blocks, where the precharge/evaluate timing and charge retention are managed carefully.
• Understanding the level pays off in debug. Reading a netlist, a cell, or a custom block — and reasoning about strength and charge — draws on exactly this chapter.

6. Common Mistakes

1. Hand-modeling functional logic at the switch level — verbose and unsynthesizable; use RTL (§4).
2. Forgetting dynamic nodes need refresh — a precharged node leaks and must be re-evaluated/kept (§3).
3. Expecting switch-level to synthesize to cells — it models transistors, not synthesizable RTL (§4).

7. Interview Q&A

8. Exercises

Exercise 1 — Full-adder logic

Write the boolean expressions for sum and cout of a full adder, and state which switch-level structures (compound gate, transmission gates) typically implement each.

Exercise 2 — Dynamic phases

For a dynamic gate, describe what happens during (a) precharge (clock low); (b) evaluate (clock high).

Exercise 3 — RTL vs switch-level

Write the one-line RTL for a full adder, and explain why it is preferred over the transistor-level version for digital design.

9. Summary

The switch level scales to full circuits, with a firm limit:

• CMOS full adder — compound complementary carry (majority/mirror) + transmission-gate sum XOR; built from the chapter's primitives.
• Dynamic logic — precharge/evaluate, NMOS-only logic network, charge-held output; fast/dense but needs refresh.
• The limit — switch-level is reference for custom cells and specialized circuits; digital systems are designed in RTL and synthesized to cells.

Chapter 12 — and the gate/switch-level reference arc — complete

This closes Chapter 12 — Switch-Level Modeling and, with Chapter 11, the gate-level and switch-level reference arc. You can now read circuits at the lowest abstractions — gate primitives and netlists (Chapter 11), MOS switches, CMOS structures, and strength resolution (Chapter 12) — which is what these levels are for: understanding synthesized netlists, standard cells, and custom blocks.

But this is not how you design. The RTL core now resumes at the level digital systems are actually built — and reaches its single most important chapter:

Chapter 14 Behavioural Modeling — always blocks, initial, blocking vs non-blocking assignment, combinational vs sequential inference, if/case, loops, generate, and the clocked logic that holds state.

Behavioural modeling completes the RTL core: combinational dataflow (Chapter 13) plus procedural, clocked behavioural logic describe any synchronous digital design — registers, counters, FSMs, and pipelines included. It is where you stop reading hardware and start designing it at its most productive level.

Related Tutorials

• Practical CMOS Circuits — Chapter 12.4; the building blocks these examples scale.
• Drive Strength and Resolution — Chapter 12.3; the strength/charge behind dynamic logic.
• Dataflow Practical Examples — Chapter 13.2; the full adder and mux at the RTL level.
• RTL Designing — Chapter 3; the level you design at, above gate and switch.