Verilog Operators & Operands — Chapter 10 Overview

Chapter 10 · Operators & Operands (Overview)

1. The Engineering Problem

By the end of Chapter 9 you could build a clean, verified module — a box with an interface and a hierarchy. But look inside that box and there is nothing yet: you can declare an 8-bit input a and an 8-bit input b, but you have no way to add them. You can store values; you cannot compute with them. A design module with no computation is an empty shell.

Data types let you hold values; modules let you organize them. Operators are how you transform them — and without operators, a design computes nothing.

This is the gap Chapter 10 fills, and it is the entry to the RTL core. Everything from here forward is about describing what a circuit computes. The atoms of that description are expressions — combinations of operators and operands — and the first thing to understand is unlike anything in software: in hardware, a + b is not an instruction that runs, it is an adder that exists. Writing operators is drawing hardware. This chapter teaches the vocabulary of computation; the sub-pages teach each operator; and the mental shift — operators are hardware — starts here.

2. What Is an Operator? An Operand?

An operator is a symbol that performs a computation; an operand is a value the operator acts on. Together they form an expression that produces a result.

//        operand   operator   operand
   sum  =    a    +     b      ;        // expression: a + b
 
//   the result (sum) is itself a value that can be an operand:
   y    = (a + b) * c ;                 // (a + b) is an operand of *

• An operator — +, &, <, ?:, and the rest — defines what computation happens.
• An operand — what the operator acts on. Operands can be constants (8'd5), nets (wire a), variables (reg b), a single bit (a[3]), a slice (a[7:4]), a concatenation ({a,b}), or the result of another expression. (§6 lists them.)
• An expression — operators applied to operands — produces a value, which can itself be an operand in a larger expression.

Expressions are the computation layer of RTL. They live inside continuous assignments (assign, Chapter 13) and procedural blocks (always, Chapter 14) — the homes you will meet next — but the computation itself is always an expression of operators and operands. Master operators and you can describe any combinational function.

3. Mental Model — Every Operator Infers Hardware

Visual A — operators are the computation layer

4. The Hardware View — Operators Become Gates

Make the mental model concrete. Each operator class maps to a recognizable hardware primitive:

Two lessons jump out. First, some operators are nearly free — a constant shift, a concatenation, and a replication are just wiring, costing no gates. Second, some are expensive — a multiplier or divider dominates a block's area and timing. An engineer who writes a * b casually where a shift-add would do has made a real silicon decision without noticing. This is why the software habit of treating all operators as equal must be unlearned: in RTL, the operator you pick is the hardware you get. (Each sub-page quantifies its operator's cost.)

Visual B — the operator family tree

5. The Operator Families

Verilog's operators fall into ten families. This overview names each with its hardware; the sub-pages drill them.

Two pairs are the classic confusion sources, flagged here and drilled in their sub-pages:

• Logical (&&) vs Bitwise (&). Logical operators reduce each whole operand to a single true/false and combine those; bitwise operators combine every bit in parallel. 4'b0010 && 4'b0001 is 1 (both nonzero → true); 4'b0010 & 4'b0001 is 4'b0000 (per-bit AND). Different operators, different hardware, a top beginner trap.
• Equality (==) vs Case-equality (===). == is the synthesizable arithmetic equality; === also compares x and z bits exactly and is simulation-only. Using === in synthesizable RTL is a mistake (10.8).

6. Operands — What Operators Act On

An operator is only half an expression; the operands are the other half. Verilog operands come in several forms:

• Constants / literals — 8'd5, 4'hF, a parameter (Chapter 6).
• Nets and variables — a wire or reg (Chapter 5), the everyday operands.
• Bit-select — a single bit of a vector, a[3].
• Part-select — a contiguous slice, a[7:4].
• Concatenation — several values joined as one operand, {a, b}.
• A sub-expression — the result of one expression feeding another, (a + b).
• A function call — a value returned by a function (Chapter 15).

The operand forms matter because they determine the width of an expression, and width determines the hardware (§8). Selecting a[3] is a 1-bit operand; a[7:4] is a 4-bit operand; {a, b} is the sum of their widths. The sub-pages show how each operator combines with these operand forms.

7. Precedence — A Preview

When several operators appear in one expression, precedence decides the order of evaluation, exactly as in arithmetic where * binds tighter than +.

   y = a + b * c ;        // * binds tighter → a + (b * c), not (a + b) * c
   y = a & b | c ;        // & binds tighter than | → (a & b) | c

Getting precedence wrong builds the wrong hardware silently — the expression compiles, but computes something other than intended. The robust habit is to parenthesize explicitly when an expression mixes operator families, rather than relying on memory. The full precedence table and its traps are Chapter 10.1, the first sub-page — appropriately, since precedence governs every multi-operator expression that follows.

8. Width and Signedness — A Preview

Every Verilog expression evaluates in a context that has a width and a signedness, and that context shapes the hardware produced:

• Width. An expression has a bit width derived from its operands and its destination. If the result is wider than the destination it is truncated; if narrower it is extended. An 8-bit + builds an 8-bit adder; assigning it to a 4-bit target drops the top bits. Width mismatches are a major silent-bug class.
• Signedness. Whether operands are signed (integer, signed reg) or unsigned changes how comparisons and shifts behave — a signed < and an unsigned < build different comparators, and an arithmetic shift (>>>) differs from a logical shift (>>).

These two — width and signedness — are the context that turns the same operator into different gates, and they are the source of many of the operator traps the sub-pages catalog. The data-type chapters (Chapter 5) established signedness and width; this chapter is where they start governing computation. For now, hold the rule: an expression's width and sign context are part of the hardware it builds.

Visual C — operator to hardware

9. What This Chapter Covers

Chapter 10 drills each operator family across eleven sub-pages. This overview names them; each gets its own deep-dive with hardware, examples, and traps.

Visual D — the Chapter 10 roadmap

10. Industry Perspective

• Expressions are everywhere. Every datapath, every comparator, every mux, every address calculation is an expression of operators. Operators are not a corner of Verilog — they are the substance of combinational RTL.
• Operator choice is a micro-architecture decision. Choosing a * b versus a shift-add, or a wide == versus a structured compare, sets area and timing. Experienced RTL engineers read an expression and see its gates and its critical-path delay.
• Synthesis maps operators to optimized hardware. A synthesizer turns + into a carry-lookahead or ripple adder, * into an optimized multiplier, picking implementations to meet timing — but it builds the operator you wrote. The engineer chooses the operation; the tool chooses the gate-level realization.
• Width and signedness bugs are common and costly. Silent truncation, unintended sign extension, and signed/unsigned comparison surprises are among the most frequent RTL defects — which is why every sub-page in this chapter foregrounds them.

11. Common Misconceptions

"Operators are free, like in software." False. Every operator infers hardware with real area and delay. a * b is a large multiplier; a + b is an adder; a constant shift is free wiring. The operator you write is the silicon you get — operator choice is a design decision, not a costless convenience.

"Logical and bitwise operators are interchangeable." False. && (logical) reduces each whole operand to true/false and combines those into one bit; & (bitwise) ANDs every bit in parallel across the vectors. They build different hardware and give different results — 4'b0010 && 4'b0001 is 1, but 4'b0010 & 4'b0001 is 4'b0000. Confusing them is a top beginner bug (10.3/10.4).

"Width doesn't matter — the tool figures it out." False. An expression's width is determined by its operands and destination, and a mismatch silently truncates or extends. A 9-bit sum assigned to an 8-bit target drops the carry. Width is part of the hardware, and width bugs are silent (§8).

"Signedness is a software detail." False. Signed vs unsigned changes how comparisons and shifts behave and what gates are built — a signed < differs from an unsigned <, and >>> differs from >>. Getting signedness wrong produces a working-looking design that computes the wrong thing on negative or large values (§8, 10.6/10.7).

12. Summary

Chapter 10 opens the RTL core — the part of Verilog that describes computation. Until now you could store and organize data; operators are how you transform it, and they are the atoms of combinational logic.

The core ideas:

• Operators compute; operands are what they act on; expressions are the result. Expressions are the computation layer that lives inside assign and always (Chapters 13–14).
• Every operator infers hardware. + is an adder, * a multiplier, < a comparator, & AND gates, ?: a multiplexer. The operator you write is the hardware you get — with real area and delay cost.
• Ten operator families — arithmetic, logical, bitwise, reduction, relational, shift, equality, replication, concatenation, conditional — each building a recognizable primitive, each a sub-page of this chapter.
• Some operators are free wiring (constant shift, concatenation, replication); some are expensive (multiplier, divider). Operator choice is a silicon decision.
• Width and signedness are part of the hardware — they shape the gates an expression builds and are the source of many operator traps; precedence governs every multi-operator expression.

The mindset this chapter instils, carried into the whole RTL core: writing an expression is drawing combinational hardware. Read every operator as the block it becomes.

The first sub-page is where multi-operator expressions begin: Chapter 10.1 Operators Precedence — the rules that decide what a + b * c actually computes, and the parenthesization discipline that keeps the hardware you build the hardware you meant. From there the chapter drills each family in turn, and the RTL core continues into dataflow (assign, Chapter 13) and procedural logic (always, Chapter 14), where these expressions become real circuits.

Related Tutorials

• Design & Testbench Creation — Chapter 9 overview; the modules these expressions will fill with computation.
• reg — Chapter 5.2.1; the variables that serve as operands and hold expression results.
• parameter — Chapter 6.1; constant operands that configure expression widths.
• RTL Designing — Chapter 3; the register-transfer model whose combinational half these operators build.