Gate-Level Modeling in Verilog — Chapter 11 Overview

Chapter 11 · Gate-Level Modeling (Overview)

1. The Engineering Problem

A synthesis tool reads your RTL and produces a netlist — and that netlist is gate-level Verilog: pages of primitive gates (or standard-cell instances) wired together by nets. To read synthesis output, debug a gate-level simulation, or understand a cell library, you need to read structural modeling. The question this short chapter answers:

How does Verilog describe a circuit as interconnected gates — the netlist level — and when does that matter, given that you write RTL in dataflow and behavioural styles?

Gate-level modeling is the answer: build-in gate primitives (and, or, not, xor, …) instantiated and wired by nets, describing a circuit structurally rather than by expression or behaviour. You rarely author new designs this way — it is verbose and low-level — but it is the form synthesis outputs, the form libraries describe cells in, and the historical root of the language. This chapter is reference: it teaches the gate primitives and their delays so you can read and reason about netlists, not so you write RTL at the gate level.

2. What Is Gate-Level (Structural) Modeling?

Structural modeling describes a circuit by what it is made of and how it is connected — gate instances and the nets between them — rather than by what it computes (dataflow) or how it behaves (behavioural):

   // A 2:1 mux, structurally — gates wired by nets:
   wire nsel, a_sel, b_sel;
   not  (nsel, sel);
   and  (a_sel, a, nsel);
   and  (b_sel, b, sel);
   or   (y, a_sel, b_sel);

This is the same mux that dataflow writes as `assign y = sel ? a : b;` — but spelled out as four gate instances and three internal nets. The structural form mirrors a schematic exactly: each primitive is a gate symbol, each net a wire. It is precise and low-level — and far more verbose than the one-line dataflow equivalent, which is why new RTL is not written this way.

3. Mental Model — A Netlist of Wired-Together Gates

Visual A — the three modeling styles, gate-level at the bottom

4. The Built-In Gate Primitives

Verilog provides a set of built-in gate primitives — logic gates ready to instantiate, no definition needed. The families (drilled in 11.1):

   and  (y, a, b, c);        // y = a & b & c   (output first, then inputs)
   or   (y, a, b);           // y = a | b
   not  (y, a);              // y = ~a
   xor  (y, a, b);           // y = a ^ b
   bufif1 (y, a, en);        // y = en ? a : 1'bz   (tri-state buffer)

The convention: the output terminal comes first, followed by the inputs. Instances may be named (and g1 (...)) or anonymous, and may carry drive strengths and delays. These primitives are the alphabet of structural modeling; 11.1 drills their syntax and use.

5. When Gate-Level Modeling Is Used

Reference-appropriate context — where you actually encounter gate-level:

• Synthesized netlists. Synthesis converts RTL into a gate-level (standard-cell) netlist — the design you tape out is gate-level structural Verilog. Reading it requires understanding this chapter.
• Gate-level simulation (GLS). After synthesis, the netlist is simulated (often with back-annotated delays from SDF) to verify the gates behave like the RTL — a gate-level activity.
• Standard-cell and IP libraries. Library cells are described structurally (and with timing); understanding primitives and gate delays (11.2) is needed to read them.
• Teaching and small structural blocks. Gate-level is a clear way to learn how gates compose, and occasionally a tiny structural block (a specific gate arrangement) is hand-written.

You do not write new functional RTL at the gate level — it is verbose and the tool infers gates from dataflow/behavioural far better. This chapter equips you to read the gate level, which is the common need.

6. What This Chapter Covers

Visual B — the Chapter 11 roadmap

7. Common Misconceptions

"Gate-level modeling is how you write RTL." False. New RTL is written in dataflow (Chapter 13) and behavioural (Chapter 14) styles — far more concise and maintainable. Gate-level is the form synthesis outputs and the level you read, not the level you author functional design at.

"Gate primitives need to be defined first." False. and, or, not, etc. are built into the language — instantiate them directly, no module definition needed (unlike user-defined primitives, Chapter 16).

"Gate-level is faster or better hardware." Misleading. Synthesis produces a better gate-level netlist from your RTL than hand-instantiated gates would, because it optimizes across the whole design. Hand gate-level is lower-level, not higher-quality.

8. Summary

Gate-level (structural) modeling describes a circuit as interconnected built-in gate primitives wired by nets — a schematic in text, the lowest modeling abstraction.

The core ideas:

• Instantiate gates, wire them with nets — and (y, a, b); and the like; output terminal first, then inputs.
• It is the netlist level — synthesized designs, gate-level simulation, and library cells are all structural gate-level Verilog.
• It is reference, not the way you author RTL — dataflow and behavioural styles are how new design is written; gate-level is what you read.
• The built-in primitives — multi-input logic (and/or/xor/…), buffers/inverters (buf/not), tri-state (bufif/notif) — are the alphabet of structural modeling.

The next sub-page drills the primitives: Chapter 11.1 Pre-defined Gate Primitives covers the built-in gates in detail — syntax, terminal ordering, multi-input and multi-output forms, tri-state gates, and building small circuits structurally — followed by 11.2 Gate Delays, the timing specifications on gates. After this reference chapter, the RTL core continues with the constructs you actually design in: behavioural modeling (Chapter 14).

Related Tutorials

• Data-Flow Modeling — Chapter 13; the expression-level abstraction above gate-level.
• RTL Designing — Chapter 3; the register-transfer level synthesis maps down to gates.
• wire and tri Nets — Chapter 5.1.1; the nets that wire gate primitives together.
• Module Instantiation — Chapter 9.2; instantiation, of which gate primitives are the built-in case.