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Verilog · Chapter 12.2.2 · Switch-Level Modeling

CMOS Logic Gates in Verilog — Inverter, NAND & NOR at the Switch Level

This topic builds CMOS logic gates at the transistor level, the inverter, NAND, and NOR, from complementary transistor networks. Every static CMOS gate is two networks: a PMOS pull-up network that connects the output to power to drive a strong 1, and a complementary NMOS pull-down network that connects the output to ground to drive a strong 0. For any input combination exactly one network conducts, so the output is always full-strength. The structure of each network encodes the logic, with transistors in series implementing an AND and transistors in parallel implementing an OR, and the two networks are duals of each other. This page shows the inverter, NAND, and NOR as switch-level pmos and nmos networks, making concrete how CMOS gates are constructed and how standard cells are structured.

Foundation13 min readVerilogCMOSLogic GatesSwitch-LevelPull-Up Network

Chapter 12 · Section 12.2.2 · Switch-Level Modeling

1. The Engineering Problem

A CMOS gate is not a single primitive — it is a structure of complementary transistors. To model one at the switch level, or to read a standard cell, you need to know how the transistors are arranged to implement a given logic function:

Every static CMOS gate is a PMOS pull-up network (to power, drives a strong 1) and a complementary NMOS pull-down network (to ground, drives a strong 0). Series transistors implement AND; parallel transistors implement OR; the two networks are duals.

This page builds the inverter, NAND, and NOR from pmos/nmos switches, making the pull-up/pull-down structure concrete.

2. Mental Model — Two Complementary Networks

3. The CMOS Inverter

The simplest gate — one PMOS pull-up, one NMOS pull-down:

cmos-inverter.v
Azvya Education Pvt. Ltd.VLSI Mentor
Snippet
module cmos_inverter (input a, output y);
    supply1 vdd;
    supply0 gnd;
    pmos (y, vdd, a);     // a=0 → pull y up to strong 1
    nmos (y, gnd, a);     // a=1 → pull y down to strong 0
endmodule

When a = 0, the PMOS conducts (PMOS on at gate 0) and drives y to a strong 1 from vdd; the NMOS is off. When a = 1, the NMOS conducts and drives y to a strong 0 from gnd; the PMOS is off. Exactly one transistor drives y for each input — a full-strength inverter (y = ~a). This is the canonical CMOS structure.

Visual A — the CMOS inverter

CMOS inverter structurepowersupply1pmos (y, vdd, a)pull-up · on at a=0nmos (y, gnd, a)pull-down · on at a=1groundsupply0y = ~afull-strength output12
A CMOS inverter: a PMOS from power to the output and an NMOS from the output to ground, both gated by the input. Input 0 turns the PMOS on, driving a strong 1; input 1 turns the NMOS on, driving a strong 0. Exactly one conducts per input, so the output is full-strength — the basic complementary-pair structure.

4. CMOS NAND and NOR — Series and Parallel

The series/parallel rule builds multi-input gates. For a 2-input NAND (y = ~(a & b)):

  • PDN (NMOS, to ground): output is 0 only when a AND b are both 1 → NMOS transistors in series (both must conduct to pull down).
  • PUN (PMOS, to power): output is 1 when a OR b is 0 → PMOS transistors in parallel (either can pull up).
cmos-nand.v
Azvya Education Pvt. Ltd.VLSI Mentor
Snippet
module cmos_nand (input a, b, output y);
    supply1 vdd;  supply0 gnd;
    wire n1;
    // PUN: two PMOS in parallel (either a=0 or b=0 pulls y up)
    pmos (y, vdd, a);
    pmos (y, vdd, b);
    // PDN: two NMOS in series (both a=1 and b=1 pull y down)
    nmos (y,  n1, a);
    nmos (n1, gnd, b);
endmodule

A 2-input NOR (y = ~(a | b)) is the dual: NMOS in parallel (either input pulls down), PMOS in series (both must be 0 to pull up). The pattern generalizes: the PDN realizes the function's 0-conditions (series for AND, parallel for OR), and the PUN is its dual.

5. Industry Perspective

  • Every static CMOS cell is a PUN/PDN pair. Reading a standard-cell schematic is reading complementary pull-up/pull-down networks — exactly this structure.
  • Series/parallel encodes the logic. Series = AND, parallel = OR; the transistor topology is the boolean function. This is how cell designers build gates.
  • Full-strength output, no static current. The complementary structure drives the output strongly in both directions and (in steady state) draws no DC current — the reason CMOS dominates.
  • You read this, you do not author it. Digital design is RTL synthesized to these cells; switch-level CMOS structure is reference for understanding what the cells are.

6. Common Mistakes

  1. Series/parallel swapped — NAND has series NMOS / parallel PMOS; NOR is the dual (§4).
  2. Non-complementary networks — if both networks conduct (or neither) for some input, the output shorts power-to-ground or floats (§2).
  3. Wrong control polarity — PMOS pull-up conducts on low inputs, NMOS pull-down on high (§3).
  4. Missing power/ground nets — the PUN connects to supply1, the PDN to supply0 (§3).

7. Debugging Lab

One CMOS-gate debug post-mortem

8. Interview Q&A

9. Exercises

Exercise 1 — Inverter trace

For the CMOS inverter, state which transistor conducts and the output value for (a) a = 0; (b) a = 1.

Exercise 2 — NAND vs NOR structure

State the NMOS and PMOS arrangement (series or parallel) for: (a) a 2-input NAND; (b) a 2-input NOR.

Exercise 3 — Build a gate

Sketch (in nmos/pmos instances) the pull-down and pull-up networks for a 2-input NOR.

10. Summary

A static CMOS gate is a complementary transistor structure:

  • PMOS pull-up network (to power) drives a strong 1; NMOS pull-down network (to ground) drives a strong 0; the two are duals, exactly one conducting per input.
  • Series = AND, parallel = OR — the topology encodes the function.
  • Inverter = one PMOS pull-up + one NMOS pull-down; NAND = series NMOS / parallel PMOS; NOR = the dual.

The next sub-topic covers the both-values pass structure: Chapter 12.2.3 Transmission Gates builds the NMOS+PMOS (or cmos/tranif) gate that passes both logic values at full strength — the fix for pass-transistor degradation.