Practical CMOS Circuits in Verilog — Tri-State, Latch, Mux & Complex Gates

Chapter 12 · Section 12.4 · Switch-Level Modeling

1. The Engineering Problem

Beyond the basic inverter and NAND/NOR (12.2.2), real CMOS design uses a handful of standard structures — tri-state drivers, transmission-gate latches and muxes, and compound AOI/OAI gates. To read or model these, you assemble the switch primitives into working circuits:

Practical CMOS circuits are the switch-level building blocks composed into useful hardware: a tri-state buffer, a transmission-gate latch, a transmission-gate mux, and complex single-stage gates.

This page builds each, applying the strength and switch behaviour of the earlier sections.

2. The Tri-State Buffer

A tri-state buffer drives its output when enabled and floats (z) when disabled — a CMOS driver gated by an enable:

module tristate_buf (input a, en, output y);
    supply1 vdd;  supply0 gnd;
    wire pu, pd;
    // enable-gated pull-up and pull-down: drive only when en=1
    // (a simplified switch-level model)
    nmos (y, gnd, pd);          // pull low when pd active
    pmos (y, vdd, pu);          // pull high when pu active
    // pu/pd derived so both are inactive (y floats) when en=0
    // ... enable logic gates pu and pd ...
endmodule

Conceptually, the tri-state buffer is a CMOS output stage whose pull-up and pull-down are both disabled when en = 0, leaving y at high-impedance (z). When en = 1, it drives y = a at full strength. The Verilog bufif1 primitive (12.2 / Chapter 11) models this directly: `bufif1 (y, a, en)` — drive when enabled, float when not. Tri-state buffers build buses where multiple drivers share a net under mutually-exclusive enables (strength resolution, 12.3, keeps the bus defined).

3. The Transmission-Gate Latch

A level-sensitive latch built from a transmission gate and feedback:

module tg_latch (input d, clk, output q);
    wire qn;
    // transmission gate passes d into the storage node when clk=1
    nmos (q, d, clk);  pmos (q, d, ~clk);     // TG: open when clk=1
    // feedback inverter pair holds the value when clk=0 (TG closed)
    not (qn, q);
    nmos (q, qn_held, ~clk);  pmos (q, qn_held, clk);   // feedback path (conceptual)
endmodule

When clk = 1 the input transmission gate is open and q follows d (transparent); when clk = 0 it closes and a feedback path holds the last value (storage). This transparent-when-high latch is a canonical custom-CMOS storage element — the transmission gate provides the controlled, full-strength path (12.2.3), and the feedback provides the hold. (The exact feedback structure varies; the principle is pass-when-open, hold-when-closed.)

Visual A — transmission-gate latch

4. The Transmission-Gate Multiplexer

Full-strength selection (the clean version of the pass-transistor mux, 12.2.1/12.2.3):

module tg_mux2 (input in0, in1, sel, output y);
    // each leg is a transmission gate; complementary sel enables one
    nmos (y, in0, ~sel);  pmos (y, in0,  sel);   // in0 when sel=0
    nmos (y, in1,  sel);  pmos (y, in1, ~sel);   // in1 when sel=1
endmodule

Each input passes through its own transmission gate, with complementary sel enabling exactly one at a time, so the selected input reaches y at full strength for both logic values. This is the standard transmission-gate mux — compact and clean, widely used in custom CMOS where a full static-CMOS mux would be larger.

5. Complex Gates — AOI and OAI

CMOS realizes compound logic in a single complementary stage. An AND-OR-Invert (AOI) gate computes ~((a & b) | c) in one gate:

• PDN (NMOS): pulls down when (a AND b) OR c is true → NMOS a,b in series, that group in parallel with NMOS c.
• PUN (PMOS): the dual → PMOS a,b in parallel, that group in series with PMOS c.

// AOI21: y = ~((a & b) | c) — one complementary CMOS stage
module aoi21 (input a, b, c, output y);
    supply1 vdd;  supply0 gnd;
    wire n1, p1;
    // PDN: (a series b) parallel c
    nmos (y, n1, a);  nmos (n1, gnd, b);   // a-b series
    nmos (y, gnd, c);                       // c parallel
    // PUN: (a parallel b) series c
    pmos (y, p1, c);
    pmos (p1, vdd, a);  pmos (p1, vdd, b); // a-b parallel, in series with c
endmodule

AOI/OAI gates are efficient because they implement a multi-level boolean function in one CMOS stage (one inversion), saving transistors and delay versus separate gates. They are workhorses of standard-cell libraries — and the series/parallel duality of 12.2.2 generalizes to build them.

6. Industry Perspective

• Tri-state, latches, muxes, and AOI/OAI are standard cells. A library is full of these structures; reading them is reading switch-level CMOS.
• Transmission-gate logic is compact. TG muxes and latches use fewer transistors than full static CMOS, common in custom datapaths and storage.
• AOI/OAI save area and delay. Compound single-stage gates are preferred by synthesis and cell designers for multi-level functions.
• Reference, not authoring. You design in RTL and let synthesis pick these cells; switch-level understanding is for reading them.

7. Common Mistakes

1. Tri-state with both networks active — must float (both off) when disabled; use bufif or gate both networks (§2).
2. Latch with no hold path — without feedback, the storage node floats when the TG closes (§3).
3. TG-mux both legs enabled — contention; complementary enables select one (§4).
4. AOI series/parallel swapped — PDN realizes the function's pull-down condition; PUN is its dual (§5).

8. Debugging Lab

module tg_latch (input d, clk, output q);
  // Input transmission gate, but NO feedback to hold the value.
  nmos (q, d, clk);
  pmos (q, d, ~clk);         // q follows d when clk=1
  // (no feedback path)
endmodule

// When clk=1, q follows d (transparent) — fine. But when clk=0, the
// transmission gate closes and NOTHING drives q — the storage node floats
// at z (or holds charge briefly then drifts to x). There is no hold.

module tg_latch (input d, clk, output q);
  wire qn, held;
  nmos (q, d, clk);  pmos (q, d, ~clk);      // capture when clk=1
  not (qn, q);
  not (held, qn);                             // held = q (buffered)
  nmos (q, held, ~clk);  pmos (q, held, clk); // feedback holds when clk=0
endmodule

// The feedback transmission gate (enabled when clk=0) drives q with its
// held value, so the latch stores when the input gate is closed.

9. Interview Q&A

10. Exercises

Exercise 1 — Tri-state states

For a tri-state buffer bufif1 (y, a, en), give y for (a) en=1, a=0; (b) en=1, a=1; (c) en=0.

Exercise 2 — Latch behaviour

For a transmission-gate latch transparent when clk=1: what does q do when (a) clk=1; (b) clk=0?

Exercise 3 — Build a TG mux

Write a 2:1 transmission-gate mux selecting a/b on sel.

Exercise 4 — AOI structure

Give the NMOS pull-down arrangement (series/parallel) for y = ~((a & b) | c).

11. Summary

Practical CMOS circuits compose the switch primitives into standard structures:

• Tri-state buffer — driver gated by enable; floats (z) when disabled (bufif1).
• Transmission-gate latch — TG capture path + feedback hold; transparent when open, stores when closed.
• Transmission-gate mux — one TG per input, complementary enables; full-strength selection.
• Complex gates (AOI/OAI) — multi-level logic in one complementary stage; efficient standard cells.

The discipline this page instils:

• Tri-state floats when disabled (both networks off); a keeper holds the bus.
• A latch needs a hold path (feedback), not just a capture path.
• Compound gates use series/parallel duality to realize multi-level functions in one stage.

The final switch-level page scales up: Chapter 12.5 Advanced Examples builds larger transistor-level circuits — a full adder, dynamic logic, and more complex CMOS structures.

Related Tutorials

• Transmission Gates — Chapter 12.2.3; the pass structure in the latch and mux.
• CMOS Logic Gates — Chapter 12.2.2; the complementary-network structure AOI extends.
• Drive Strength and Resolution — Chapter 12.3; how the tri-state bus resolves.
• Dataflow Practical Examples — Chapter 13.2; the same functions at the dataflow level.