Data-Flow Modeling in Verilog — Chapter 13 Overview

Chapter 13 · Data-Flow Modeling (Overview)

1. The Engineering Problem

You finished Chapter 10 able to write any combinational expression — a + b, sel ? x : y, (addr >= BASE) && (addr < LIMIT), {cout, sum}. But an expression by itself is inert: it is a description of a computation, not yet a circuit in your design. The question that opens the RTL core's second chapter is:

How does an operator expression become actual, always-on hardware inside a module — a circuit that continuously computes, in parallel with everything else?

The answer is the continuous assignment, assign. Writing `assign y = a + b;` does not "run" the addition once — it wires an adder permanently between a, b, and y, so that y always equals a + b: change a or b, and y updates immediately. This is dataflow modeling — describing hardware by how data flows through expressions — and it is where every operator from Chapter 10 finally becomes a circuit.

Dataflow is the simplest of the three ways to describe hardware, and the right one for all combinational logic: muxes, decoders, adders, encoders, masks, and the glue that connects a design together. This chapter is its introduction; the overview here frames the model, and the sub-pages drill the mechanics.

2. What Is Dataflow Modeling?

Dataflow modeling describes a circuit by the movement and transformation of data — what each output is, as an expression of the inputs — rather than by listing gates (gate-level) or by writing procedural steps (behavioural). The vehicle is the continuous assignment:

   assign sum     = a + b;                  // an adder
   assign y       = sel ? in1 : in0;        // a multiplexer
   assign in_range = (v >= LO) && (v <= HI); // a range comparator
   assign masked  = data & MASK;            // a mask

Each assign states what a net equals as an expression of other signals. The synthesizer reads that expression and builds the combinational hardware that computes it — an adder, a mux, a comparator. You describe the function; the tool builds the gates. This is a higher level of abstraction than drawing gates, and exactly the level at which combinational logic is naturally expressed.

3. Mental Model — A Continuous Assignment Is Always-On Combinational Hardware

Visual A — operators become dataflow hardware

4. The Three Modeling Styles

Verilog offers three abstraction levels for describing hardware. Dataflow is the middle one, and the right one for combinational logic:

• Gate-level is the lowest level — you name each gate and connect them, as in a netlist. It is verbose and rarely written by hand for new RTL (covered as reference in Chapter 11).
• Dataflow raises the abstraction to expressions: you write `assign y = a + b;` and the tool builds the adder. This is the sweet spot for combinational logic — concise, readable, and exactly matched to the operators of Chapter 10.
• Behavioural (Chapter 14) raises it further to procedural descriptions in always blocks, which can express clocked, sequential logic (state, registers, FSMs) that dataflow cannot.

A real design mixes styles, but dataflow is where combinational logic lives, and it is the natural next step after learning the operators.

Visual B — the three modeling styles

5. The Hardware View — Concurrent, Always-On Logic

A dataflow design is a collection of continuous assignments running in parallel, each a small combinational circuit. This concurrency is the defining hardware fact and the biggest shift from software thinking:

   assign p = a & b;        // these three assignments are ALL active
   assign q = p | c;        // simultaneously — p, q, r are all live at once
   assign r = q ^ d;        // reordering them changes NOTHING

These three look like sequential steps, but they are three pieces of hardware running at the same time. p continuously equals a & b; q continuously equals p | c (tracking p's changes); r continuously equals q ^ d. Writing them in any order builds the identical circuit, because they are concurrent connections, not ordered statements. When an input changes, the change ripples through the connected assignments combinationally — exactly as signals propagate through a real gate network. Understanding that assign statements are concurrent hardware, not sequential code, is the core mental shift of dataflow modeling.

6. Continuous Assignment Basics — A Preview

The mechanics — drilled in 13.1 — in brief:

   wire y;
   assign y = a & b;                 // explicit continuous assignment
 
   wire z = c | d;                   // implicit form: assign at declaration
 
   // the LHS is a NET (wire); the RHS is any expression of signals/constants

Three points the sub-page expands:

• The LHS must be a net (wire), driven continuously by the assignment — not a reg (those are procedural, Chapter 14).
• The RHS is any expression — the full operator vocabulary of Chapter 10.
• One driver per net, normally — a net continuously driven by two assignments has two drivers and resolves by contention (the net-resolution rules of Chapter 5); normal combinational logic uses one assign per net.

7. Dataflow vs Procedural — A Preview of Chapter 14

The contrast that orients the rest of the RTL core:

• Dataflow (assign, this chapter) — continuous and concurrent; describes combinational logic by expression; the LHS is a net that always reflects the RHS.
• Procedural (always, Chapter 14) — executed (in simulation) when triggered; describes combinational or sequential logic with statements (if, case); the LHS is typically a reg.

They are complementary: dataflow for the combinational glue and datapath expressions, procedural for clocked state and complex control. The conditional operator ?: you learned in 10.11 is the dataflow mux; its procedural twin is the if/case of an always block. This chapter does combinational dataflow; the next adds procedural and sequential logic.

8. What This Chapter Covers

Chapter 13 drills dataflow modeling across three sub-pages:

Visual C — the Chapter 13 roadmap

9. Industry Perspective

• Dataflow is the default for combinational logic. Muxes, decoders, encoders, adders, comparators, bit-field manipulation, and the glue logic that wires a design together are written as continuous assignments — concise and directly readable as the function they compute.
• assign expresses intent cleanly. A one-line `assign out = sel ? a : b;` says "this is a mux" far more clearly than gate instantiations, which is why dataflow dominates hand-written combinational RTL.
• Concurrency matches hardware. Because continuous assignments are inherently parallel, dataflow models the true concurrency of a circuit naturally — there is no artificial ordering to reason about, just connected expressions.
• Dataflow + procedural is the standard mix. Real modules combine dataflow (combinational glue, datapath expressions) with procedural always blocks (clocked state) — the two styles cover the whole of RTL.

10. Common Misconceptions

"An assign runs once, like a program statement." False. A continuous assignment is a permanent connection — the net continuously reflects the expression, updating whenever any operand changes. It is always active, not executed once.

"The order of assign statements matters." False. Continuous assignments are concurrent — all active simultaneously, independent of textual order. Reordering them builds the identical circuit. (This is the opposite of procedural statements in an always block.)

"Dataflow can model sequential logic." Misleading. Dataflow naturally models combinational logic — output as a function of current inputs, no clock, no memory. Clocked, stateful (sequential) logic needs procedural always blocks (Chapter 14). Forcing state into dataflow (with feedback) produces fragile, hard-to-synthesize logic and is not how sequential design is done.

"assign can drive a reg." False. A continuous assignment drives a net (wire). reg variables are driven by procedural assignments inside always/initial blocks. Mixing them up is a common beginner error (and a compile error).

11. Summary

Dataflow modeling describes combinational hardware by the flow of data through expressions, using the continuous assignment (assign). It is where the operators of Chapter 10 become always-on circuits.

The core ideas:

• A continuous assignment wires an expression to a net that continuously reflects it — `assign y = a + b;` makes y always equal a + b. It is a permanent connection, not a one-time statement.
• Continuous assignments are concurrent — all active in parallel, order-independent; they model the true concurrency of hardware.
• Dataflow models combinational logic — output as a function of current inputs, no clock or memory; sequential logic needs procedural always (Chapter 14).
• The LHS is a net (wire), not a reg — nets are driven continuously; regs are driven procedurally.
• Dataflow is the middle modeling style — above gate-level (Ch 11), below behavioural (Ch 14), and the natural fit for the operators of Chapter 10.

The mindset this chapter instils: an assign is a piece of combinational hardware that is always computing, in parallel with every other one — read a dataflow module as a network of connected, always-on expressions.

The first sub-page drills the mechanics: Chapter 13.1 Continuous Assignments covers the assign statement in detail — net-driving, explicit and implicit forms, the one-driver discipline, and the concurrency that makes dataflow hardware. From there the chapter builds real combinational circuits, and then the RTL core advances to Chapter 14 Behavioural Modeling — procedural always blocks, blocking versus non-blocking assignment, and the sequential, clocked logic that turns combinational expressions into stateful RTL.

Related Tutorials

• Verilog Operators & Operands — Chapter 10 overview; the expressions that live on the right of every continuous assignment.
• Conditional Operator — Chapter 10.11; the dataflow mux (?:) that continuous assignments most often carry.
• Module Structure & Elements — Chapter 9.1; the module these continuous assignments live inside.
• wire and tri Nets — Chapter 5.1.1; the nets that continuous assignments drive.