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Verilog · Chapter 12.2 · Switch-Level Modeling

Switch Level Primitives in Verilog — nmos, pmos, cmos, tran & Sources

This lesson surveys the switch-level primitives Verilog gives you to model transistors. It covers the one-directional switches nmos, pmos, and the combined cmos, their resistive variants that weaken the signal they pass, the bidirectional tran switches that model transmission gates and pass connections, and the weak pullup and pulldown sources. For each primitive you will see the syntax, the terminal order of output, data, and control, when it conducts, and the high-impedance state it enters when it is off. You will also see the transistor-level structures these primitives assemble into. This page is the gateway to four deeper sub-topics covering nmos and pmos behaviour, CMOS gates, transmission gates, and resistive switches. The goal is to read and reason about transistor-level netlists, not to write synthesizable RTL.

Foundation15 min readVerilogSwitch-LevelnmospmoscmosTransmission Gate

Chapter 12 · Section 12.2 · Switch-Level Modeling

1. The Engineering Problem

To model a transistor-level circuit — a CMOS gate, a transmission-gate mux, a pass-transistor network — you need the switch-level primitives and their exact syntax: which terminal is the output, which is the control, and how each conducts. The question:

What switch primitives does Verilog provide to model MOS transistors, and how is each instantiated and controlled?

This page surveys them — the unidirectional MOS switches, their resistive variants, the bidirectional transmission switches, and the pull sources — and the structures they build. It is the catalogue; the four sub-topics drill the behaviours and circuits in depth.

2. Mental Model — A Catalogue of Switch Devices

3. Unidirectional MOS Switches — nmos, pmos, cmos

The core switches drive an output from a data input under gate control:

mos-switches.v
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Snippet
   nmos (out, data, gate);        // out = data when gate=1, else z   (NMOS)
   pmos (out, data, gate);        // out = data when gate=0, else z   (PMOS)
   cmos (out, data, ngate, pgate);// combined: NMOS(ngate) + PMOS(pgate)
  • nmos (out, data, gate) — conducts when gate = 1, passing data to out (strong 0, weak 1, per 12.1); high-impedance when gate = 0.
  • pmos (out, data, gate) — conducts when gate = 0 (strong 1, weak 0); high-impedance when gate = 1.
  • cmos (out, data, ncontrol, pcontrol) — equivalent to an nmos and a pmos in parallel sharing out and data, with separate controls. With complementary controls it is a transmission gate (12.2.3) passing both values cleanly.

Terminal order: output, data, control(s) — distinct from logic-gate primitives (Chapter 11) where it is output then inputs. (12.2.1 and 12.2.2 drill these and CMOS gates.)

4. Resistive MOS Switches — rnmos, rpmos, rcmos

The resistive variants behave like their counterparts but reduce the strength of the passed signal:

resistive-mos.v
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Snippet
   rnmos (out, data, gate);       // like nmos, but reduces signal strength
   rpmos (out, data, gate);       // like pmos, but reduces signal strength
   rcmos (out, data, ng, pg);     // like cmos, but reduces signal strength

They model high-resistance transistors — a strong input becomes pull, a pull becomes weak, and so on down the strength scale (12.3, 12.2.4). They are used where a device deliberately weakens a signal (e.g. in some charge-sharing and ratioed circuits), and they matter in strength resolution because a resistive switch's output loses to a non-resistive driver of the original strength.

5. Bidirectional Switches — tran, tranif0, tranif1

Bidirectional switches connect two nodes in either direction — a pass connection, not a one-way drive:

bidirectional.v
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Snippet
   tran    (a, b);                // a and b are always connected (both directions)
   tranif1 (a, b, ctrl);          // connected when ctrl=1, else isolated (z)
   tranif0 (a, b, ctrl);          // connected when ctrl=0, else isolated
   // resistive versions: rtran, rtranif1, rtranif0 (reduce strength)
  • tran (a, b) — an unconditional bidirectional connection: a and b are the same node, signals pass either way.
  • tranif1 (a, b, ctrl) — connects a and b when ctrl = 1, isolates them (high-impedance) when ctrl = 0; tranif0 is the opposite polarity.
  • These model transmission gates and pass-transistor connections where a signal flows in whichever direction the surrounding circuit drives it. The resistive rtran* versions reduce strength.

Bidirectional switches have no fixed "output" — both terminals are bidirectional — which is what distinguishes them from the unidirectional MOS switches. (12.2.3 drills transmission gates.)

6. Sources — pullup and pulldown

The pull sources drive a weak constant value onto a net:

pull-sources.v
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Snippet
   pullup   (net);                // weak 1 on 'net'
   pulldown (net);                // weak 0 on 'net'
  • pullup (net) drives a pull-strength 1; pulldown (net) drives a pull-strength 0.
  • They model a pull resistor: a weak default that holds a net at a known value when no stronger driver is active, but yields to any strong driver (the strength order of 12.3). The canonical use is keeping an undriven tri-state bus or a dynamic node at a defined level rather than letting it float.

These complete the device catalogue — switches to connect, sources to hold a default.

Visual A — the switch-primitive families

Switch-level primitive families

data flow
Switch-level primitive familiesnmos / pmos /cmosunidirectional MOS switchrnmos / rpmos /rcmosresistive (reduce strength)tran / tranif0 /tranif1bidirectional (transmission)pullup / pulldownweak constant source
Four families of switch-level primitive: unidirectional MOS switches (the core devices), their resistive strength-reducing variants, bidirectional transmission switches, and the pullup/pulldown weak sources. Together they model transistor-level circuits, with node values decided by strength resolution (12.3).

7. The Sub-Topics

This parent surveys the primitives; four sub-topics go deeper:

§Sub-topicCovers
12.2.1PMOS & NMOS Behaviorthe unidirectional MOS switches in depth — conduction, strength, pass logic
12.2.2CMOS Logic Gatesbuilding CMOS gates (inverter, NAND, NOR) from complementary transistors
12.2.3Transmission Gatesthe NMOS+PMOS / cmos / tranif transmission gate that passes both values
12.2.4Resistive MOS Switchesthe r-variants and how they reduce strength

8. Industry Perspective

  • CMOS cells are unidirectional MOS networks. Standard-cell gates are NMOS pull-down + PMOS pull-up structures — nmos/pmos at the model level.
  • Transmission gates use cmos/tranif. Transmission-gate muxes and latches, common in custom CMOS, are modeled with the bidirectional switches or a cmos pair.
  • pullup/pulldown hold tri-state buses. A weak pull keeps an otherwise-floating bus or dynamic node at a defined level — a real circuit technique modeled directly by these sources.
  • Resistive switches model ratioed/charge-sharing circuits. Where a device deliberately weakens a signal, the r-variants capture the strength reduction that strength resolution then accounts for.

9. Common Mistakes

  1. Wrong terminal order — switches are (out, data, control), not output-then-inputs like logic gates (§3).
  2. Confusing unidirectional and bidirectional — nmos/pmos drive one way; tran/tranif pass either way (§5).
  3. Forgetting resistive variants reduce strength — rnmos output loses to a same-original-strength nmos (§4, 12.3).
  4. Floating tri-state nodes — use pullup/pulldown to hold an undriven net (§6).
  5. Expecting switch primitives to synthesize — they model transistors for simulation, not synthesizable RTL (overview).

10. Debugging Lab

Two switch-primitive debug post-mortems

11. Interview Q&A

12. Exercises

Exercise 1 — Name the primitive

Which primitive fits each: (a) a switch that passes data when its gate is 1; (b) a switch that passes data when its gate is 0; (c) a bidirectional connection enabled by a control; (d) a weak default 0 on a net; (e) a combined NMOS/PMOS switch.

Exercise 2 — Read the instances

State what each does: (a) nmos (y, d, en); (b) pmos (y, d, en); (c) tranif1 (x, z, c); (d) pullup (bus); (e) rnmos (y, d, en).

Exercise 3 — Fix the order

Identify and fix: (a) pmos (d, y, en) intending y = d when en=0; (b) a tri-state bus that floats to z when idle.

Exercise 4 — Choose the structure

Which primitives would you use to: (a) pass both logic values cleanly through a switch; (b) hold an idle bus at 1; (c) connect two nodes in both directions under control?

13. Summary

The switch-level primitives model MOS transistors and pass structures:

  • Unidirectional MOS — nmos (on at gate 1), pmos (on at gate 0), cmos (combined); order (output, data, control).
  • Resistive MOS — rnmos/rpmos/rcmos reduce the passed signal's strength.
  • Bidirectional — tran (always), tranif1/tranif0 (controlled) connect two nodes either way (transmission gates).
  • Sources — pullup/pulldown drive a weak constant 1/0 to hold a net.

The discipline this page instils:

  • Switch order is (output, data, control) — not output-then-inputs.
  • Use pullup/pulldown to hold tri-state/dynamic nodes from floating.
  • Resistive variants reduce strength — they lose to a same-original-strength driver.

The sub-topics drill the details: 12.2.1 PMOS & NMOS Behavior goes deeper on the unidirectional switches and pass logic, 12.2.2 CMOS Logic Gates builds gates from complementary transistors, 12.2.3 Transmission Gates covers the both-values pass structure, and 12.2.4 Resistive MOS Switches drills strength reduction. Then 12.3 Drive Strength and Resolution explains how node values are decided.