AMBA AXI · Module 18

AXI Design Interview Questions

Answer 'design an AXI X' RTL prompts live — the structured approach (clarify the spec, sketch the interface, choose the FSM, handle the handshake and corner cases), worked through a slave and a skid buffer, and the design instincts (channel independence, VALID-not-on-READY, corner-case awareness) interviewers look for.

Design questions — "design an AXI4-Lite slave," "build a skid buffer," "sketch the write FSM" — are the inverse of waveform reading (18.4): instead of interpreting a trace, you produce RTL live. They test whether you can turn a spec into a correct structure under pressure, and interviewers watch for design instincts — clarifying ambiguity, choosing a clean FSM, getting the handshake right, and surfacing corner cases unprompted. The good news: design prompts have a structured approach (clarify → interface → FSM → handshake → corners) that produces a correct sketch every time, and the AXI building blocks from Module 15 are exactly the answers. This chapter gives the approach and works it through the two most common prompts — a slave and a skid buffer — plus the instincts that distinguish a strong design answer.

1. The Structured Design Approach

Don't start writing RTL immediately — follow a structure that produces a correct design and shows your process. (1) Clarify the spec: AXI4 or AXI4-Lite? data/address widths? bursts? outstanding? — never assume; asking is a strength. (2) Sketch the interface: list the ports (the channels you need), which signals in/out. (3) Choose the FSM: the states and transitions for the control flow. (4) Handle the handshake: get VALID/READY right (the never-break rule). (5) Surface corner cases: stalls, decoupled AW/W, errors, reset — naming them unprompted is the mark of a real designer. This sequence turns an open prompt into a methodical, correct answer.

Figure 1 — the structured approach to an AXI design prompt. (1) Clarify the spec (Lite vs. full, widths, bursts, outstanding) — asking is a strength, not weakness. (2) Sketch the interface (ports/channels). (3) Choose the FSM (states and transitions). (4) Handle the handshake (VALID/READY, the never-break rule). (5) Surface corner cases (stalls, decoupled AW/W, errors, reset) unprompted. This sequence produces a correct design and demonstrates process — which is what the interviewer assesses as much as the final RTL.

2. Worked Prompt: "Design an AXI4-Lite Slave"

The most common design prompt. Clarify: AXI4-Lite (single-beat, no bursts/IDs), 32-bit data, a few registers — confirm. Interface: the five Lite channels (AW/W/B/AR/R), no *LEN/*SIZE/*ID. FSM: a small write FSM (IDLE → WRITE → RESP) and a separate read FSM (IDLE → RESP), reflecting that reads and writes are independent. Handshake: s_awready/s_wready high when ready to accept, BVALID held until BREADY; VALID never gated on READY. Corners: AW/W can arrive in either order (latch each), WSTRB byte writes, unmapped address → DECERR, read-only write → SLVERR. Sketching this (the structure from 15.1) with the corners named is the strong answer.

Figure 2 — the AXI4-Lite slave design: two independent FSMs. The write FSM (IDLE → WRITE → RESP) collects AW and W (in either order), commits the WSTRB-masked write, and emits one B response held until BREADY. The read FSM (IDLE → RESP) accepts AR and returns RDATA/RRESP held until RREADY. Keeping them separate reflects read/write independence — a key design instinct. This is the structure from Chapter 15.1, the canonical answer to the most common design prompt.

3. Worked Prompt: "Build a Skid Buffer"

A frequent prompt because it tests handshake mastery. Clarify: full-throughput, registered both directions? (Yes — that's why it's a skid, not a single register.) Interface: upstream s_* (data/valid/ready), downstream m_*. FSM/structure: a main register feeding the output and a skid (overflow) register; occupancy is EMPTY/ONE/FULL. Handshake: s_ready = !skid_valid (accept while the overflow slot is free); on output consume, promote the skid beat to main. Corners: the in-flight beat when READY toggles (the reason two registers are needed), payload stability, full-throughput steady state (the ONE self-loop). The key insight to state: two registers are the minimum for fully-registered, full-throughput — the reason the skid exists (the structure from 15.5).

Figure 3 — the skid buffer design: two registers and the EMPTY/ONE/FULL occupancy. A main register drives the output; a skid (overflow) register catches the one in-flight beat that arrives when READY toggles (registered backpressure makes the upstream see READY a cycle late). s_ready = !skid_valid; on consume, the skid beat promotes to main. The key design point to state: two registers are the minimum for a fully-registered, full-throughput handshake — which is the whole reason the skid exists (Chapter 15.5).

4. The Design Instincts Interviewers Reward

Beyond the structure, interviewers watch for instincts that signal a real designer. Channel independence: reads and writes (and address/data) proceed independently — separate FSMs, no illegal coupling. VALID ⊥ READY: never gate VALID on READY (the deadlock rule) — drive VALID independently and hold it. Corner-case awareness: surface stalls, decoupled AW/W, errors, reset unprompted — a designer who names the corners before being asked stands out. Reuse the building blocks: recognize that the prompt maps to a known primitive (a slave, a skid, a FIFO, an FSM from Module 15) rather than inventing from scratch. Parameterise sensibly: widths as parameters, derived values computed. These instincts, shown through the answer, are what distinguish a strong design candidate.

Figure 4 — the design instincts interviewers reward. Channel independence (separate read/write FSMs, no illegal coupling); VALID never gated on READY (the deadlock rule); corner-case awareness (surface stalls/decoupled-AW-W/errors/reset unprompted); reuse the building blocks (map the prompt to a known Module-15 primitive); parameterise sensibly (widths as parameters, derived values computed). Demonstrating these instincts through the answer — not just producing working RTL — is what distinguishes a strong design candidate.

5. Common Misconceptions

Myths to unlearn

"Start writing RTL immediately." Jumping into code without clarifying the spec or sketching the structure produces a messy, often-wrong design and hides your process. Follow clarify → interface → FSM → handshake → corners; the structure is half of what's assessed.
"Asking clarifying questions looks weak." The opposite — clarifying is a strength. "AXI4 or Lite? bursts? outstanding?" shows you know the design space and won't build the wrong thing. Assuming silently is the weak move.
"Get the happy path working; corners come later." Surfacing corner cases — stalls, decoupled AW/W, errors, reset — unprompted is exactly what distinguishes a real designer. The interviewer is often waiting to see if you mention them; volunteering them is a strong signal.
"Couple reads and writes into one FSM to save logic." That violates channel independence and serializes them needlessly. Separate read/write FSMs is the correct instinct — it reflects the protocol and is cleaner.
"Gate VALID on READY to simplify the handshake." The deadlock rule — never do this. VALID must be driven independently of READY. An interviewer will catch this instantly; it's the single most-watched mistake in a design answer.
"Invent the design from scratch." Most prompts map to a known primitive (a slave, skid buffer, FIFO, FSM from Module 15). Recognizing "this is a skid buffer" and reproducing the standard structure is faster and more correct than inventing — and shows you know the building blocks.

6. Debugging Insight

🔍 Debugging insight — a weak design answer skipped a step or an instinct

Diagnose a weak design answer by what it skipped:

Built the wrong thing. Skipped clarify — assumed full AXI when it was Lite, or vice versa. Fix: always ask the spec questions (Lite/full, widths, bursts, outstanding) before designing.
Messy, hard-to-follow design. Skipped the structure — jumped to RTL without sketching the interface and FSM. Fix: sketch ports and states first; the structure makes the RTL fall out cleanly.
Handshake bug (gated VALID on READY). Skipped the handshake rule. Fix: drive VALID independently, hold it until accepted; the interviewer watches for this specifically.
No corner cases mentioned. Skipped corner awareness — gave only the happy path. Fix: proactively name stalls, decoupled AW/W, errors, reset; volunteering them is a strong signal.
Coupled reads and writes. Skipped the channel-independence instinct. Fix: separate read/write FSMs.
Reinvented a known block. Skipped reuse — built a skid buffer from scratch awkwardly instead of recognizing the standard two-register structure. Fix: map the prompt to the Module 15 primitive and reproduce it.

The meta-skill: a strong design answer is the structured approach (clarify → interface → FSM → handshake → corners) executed with the instincts (independence, VALID⊥READY, corner-awareness, reuse, parameterise). A weak answer skipped a step or an instinct — diagnose which, and the fix is to add it back into the process.

7. Verification Insight

✅ Interview insight — structure plus instincts, and let the building blocks be your answers

Design prompts test whether you can produce correct RTL structure under pressure while showing design judgment — and the discipline is a structured approach executed with instincts. The approach: clarify the spec (Lite vs. full, widths, bursts, outstanding — asking is a strength), sketch the interface (the channel ports), choose the FSM (states/transitions), handle the handshake (VALID/READY, never gating VALID on READY), and surface corner cases (stalls, decoupled AW/W, errors, reset — unprompted). The instincts the interviewer is really watching for: channel independence (separate read/write FSMs), the VALID ⊥ READY rule (the single most-watched mistake), corner-case awareness (volunteering the corners is a strong signal), reuse of the building blocks (recognize the prompt maps to a Module 15 primitive — a slave, skid buffer, FIFO, or FSM — and reproduce the standard structure rather than inventing), and sensible parameterisation. The two most common prompts — "design an AXI4-Lite slave" (15.1: two independent FSMs, WSTRB writes, DECERR/SLVERR) and "build a skid buffer" (15.5: two registers, s_ready = !skid_valid, the minimum for fully-registered full-throughput) — are exactly the Module 15 building blocks, so the chapters you studied to build RTL are the answers to the design interview; the prompt is asking you to reproduce a primitive you already know. The key reframe: the design interview rewards process and judgment as much as the final RTL — clarifying questions, a clean structure, the handshake rule, and unprompted corner cases all signal a real designer, while jumping straight to messy code (even if it eventually works) signals the opposite. The connection to the job is the most direct of all the interview types: design questions are literally the work — turning a spec into correct, robust RTL with the right instincts — so practicing them is practicing design itself, and the instincts that win the interview (independence, the deadlock rule, corner awareness, reuse, parameterisation) are the same ones that produce good RTL in practice. This is the through-line of Module 18 made concrete: articulation and demonstration of understanding is the skill, and in the design round, demonstrating it means producing a structured, instinct-driven design live. Next, verification interview questions test the complementary side: how you'd verify the AXI design you can now produce.

8. Interview Questions

9. Summary

Design-interview questions ("design an AXI X") are the inverse of waveform reading — you produce RTL live — and they're made reliable by a structured approach: clarify the spec (Lite vs. full, widths, bursts, outstanding — asking is a strength), sketch the interface (channel ports), choose the FSM (states/transitions), handle the handshake (VALID/READY, never gating VALID on READY), and surface corner cases (stalls, decoupled AW/W, errors, reset — unprompted). The two most common prompts map directly to Module 15 primitives: the AXI4-Lite slave (15.1 — two independent FSMs, WSTRB writes, DECERR/SLVERR) and the skid buffer (15.5 — two registers, s_ready = !skid_valid, the minimum for fully-registered full-throughput). Recognizing that a prompt maps to a known block and reproducing it beats inventing.

Beyond the structure, interviewers reward design instincts: channel independence (separate read/write FSMs), the VALID ⊥ READY rule (the most-watched mistake), corner-case awareness (volunteering the corners), reuse of the building blocks, and sensible parameterisation. The design round assesses process and judgment as much as the final RTL — clarifying questions, a clean structure, the handshake rule, and unprompted corners all signal a real designer; jumping to messy code signals the opposite. It's the most direct job-ability test of all the interview types, because design is the work — so practicing it (sketch the blocks, internalize the approach, drill the instincts, think aloud, map prompts to primitives) is practicing engineering itself. This is Module 18's through-line made concrete: demonstrating understanding means producing a structured, instinct-driven design live. Next, verification questions test the complementary side — how you'd verify the AXI design you can now produce.

10. What Comes Next

You can now produce AXI RTL from a prompt; next, how you'd verify it:

18.6 — Verification Interview Questions (coming next) — checker, coverage, and UVM AXI prompts, the verification-side complement to the design questions, where you describe how to prove the design you'd build is correct.

Previous: 18.4 — Waveform Interpretation Questions. Related: 15.1 — A Simple AXI4-Lite Slave and 15.5 — The Skid Buffer for the two canonical design prompts, and 3.5 — Handshake Dependency & Deadlock Rules for the VALID ⊥ READY rule.

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Standards & specifications

Governing standard: Arm AMBA AXI Protocol Specification (IHI 0022)(opens Arm in a new tab)
Defines the AXI channels, handshake and ordering rules. RTL structure, interconnect topology and verification strategy are design choices this specification does not mandate.

This page also covers RTL structure, verification approach and debugging technique. Those are engineering practice built on the standard, not requirements the standard itself imposes.

Where this fits

Part of the AMBA AXI curriculum.