AXI4 Write Channel — AW, W & B Handshake

An AXI4 write is not one transfer — it is three independent handshakes on three separate channels: AW (write address), W (write data), and B (write response). Each channel uses the same VALID/READY handshake, and the channels are decoupled so a master can stream write data while the next address is still in flight. That decoupling is what gives AXI its throughput — and the dependency rules between the channels are what keep it correct. This lesson covers the three write channels, the universal handshake, the AXI4 channel-dependency rules, the BRESP response codes, and the protocol bugs you will actually see on a bus capture. Grounded in AMBA 5 AXI4 (ARM IHI 0022).

1. Engineering Problem — Why a Write Is Three Channels

A naive bus couples address and data: present the address, present the data, get an acknowledge, done. That serialises everything — the master cannot issue the next address until the current data and acknowledge have drained, and a slow responder stalls the whole bus.

AXI4 breaks the write into three independent channels so they can overlap. The master can push write data (W) before, with, or after it sends the write address (AW); it can launch a second AW while the first transaction's response (B) is still pending. Each channel advances on its own VALID/READY handshake, at its own pace. The cost of that freedom is a small set of dependency rules — which signal may wait for which — and a response channel (B) that reports whether the write actually succeeded. Get the channels and their dependencies right and you have a high-throughput, out-of-order-capable interconnect; get them wrong and you get the classic AXI deadlock where two sides each wait for the other forever.

2. Channel & Layer Placement

• Real bus: AMBA 5 AXI4 (ARM IHI 0022), the workhorse interconnect of high-performance SoCs — DRAM controllers, NVMe/PCIe bridges, GPU and accelerator fabrics.
• Layer: the AXI transaction layer. AXI has five channels — AW, W, B (write) and AR, R (read). This lesson is the write trio: AW, W, B.
• Direction: AW and W are master → slave; B is slave → master.

3. Mental Model — Independent Channels, One Handshake

The picture every engineer carries:

An AXI write is three one-directional channels, each carrying its own VALID/READY handshake, that together form one transaction. The source of a channel asserts VALID when it has put valid information on the bus; the destination asserts READY when it can accept it; the transfer happens on the rising ACLK edge where both are high. The channels are independent in time but bound by transaction order: a write isn't done until its data is accepted and the slave returns a B response. The one rule that prevents deadlock: a source must never wait for READY before asserting VALID.

Four invariants this picture preserves:

• One handshake, five channels. Learn VALID/READY once and you know all five channels — only the payload signals differ (awaddr, wdata, bresp, …).
• AW and W are decoupled. AXI4 lets the master send W data before, with, or after the AW address. The slave pairs them by transaction order, not by timing.
• B closes the transaction. A write is complete only when the slave drives a response on B and the master accepts it — BRESP says whether it succeeded.
• VALID is unconditional; READY may be conditional. The source asserts VALID based only on its own data being ready; the destination may make READY depend on VALID. The reverse is illegal and is the #1 cause of AXI hangs.

4. The VALID/READY Handshake — The State Lens

Every channel is the same three-state cycle: idle, waiting (source has data, destination not yet ready), and transfer (both high → one beat moves on this clock edge). Once a source asserts VALID it must hold it — and hold the payload stable — until the transfer completes.

5. The Wire Lens — A Single-Beat Write

The full write: the AW address handshake, the W data handshake (with WLAST marking the final beat — for a single beat, WLAST=1 on that beat), then the slave's B response, which the master accepts with BREADY.

Walking the transfers, each on a rising aclk edge where both handshake signals are high:

1. AW (address): the master drives awvalid with awaddr on the bus; the slave raises awready; the address is accepted on that edge.
2. W (data): the master drives wvalid, wdata, wstrb, and wlast; the slave raises wready; the data beat is accepted. wlast=1 marks the last (here, only) beat of the burst.
3. B (response): after it has accepted the write data, the slave drives bvalid with bresp; the master accepts it with bready. The write is now complete.

Note the slave does not drive B until it has taken the write data — that ordering is a hard rule (§7).

6. The B Response — BRESP Semantics

The write response is the slave telling the master what happened. BRESP is a 2-bit code (identical encoding to the read channel's RRESP):

7. Channel-Dependency Rules — What May Wait for What

The channels are independent, but not arbitrary. AXI4 defines exactly which handshake may depend on which, and these rules are what keep a decoupled bus correct:

• Within a channel: the source asserts VALID independently; the destination's READY may depend on VALID (wait-for-valid) or be asserted ahead of it. VALID must never depend on READY.
• AW vs W (AXI4): the master may present write data before, with, or after the write address — there is no required ordering between AW and W in AXI4. (This is a relaxation from AXI3.)
• B vs W: the slave must not assert bvalid until after it has accepted the write data — i.e. after the W-channel handshake of the last beat (wlast). A response before the data is a protocol violation.
• BREADY: the master may assert bready before or after bvalid; it must eventually assert it so the response drains.

// Minimal AXI4-Lite-style write slave — single beat, both sides' public signals.
// (Burst length / WSTRB depth are covered in axi4-bursts-and-len and
//  axi4-strobes-and-narrow-bursts; this models the single-beat handshake + BRESP.)
module axi_write_slave #(
    parameter int ADDR_W = 32,
    parameter int DATA_W = 32
) (
    input  logic                aclk,
    input  logic                aresetn,
    // ── AW: write address (master → slave) ─────────────────────────
    input  logic [ADDR_W-1:0]   awaddr,
    input  logic                awvalid,
    output logic                awready,
    // ── W: write data (master → slave) ─────────────────────────────
    input  logic [DATA_W-1:0]   wdata,
    input  logic [DATA_W/8-1:0] wstrb,
    input  logic                wlast,
    input  logic                wvalid,
    output logic                wready,
    // ── B: write response (slave → master) ─────────────────────────
    output logic [1:0]          bresp,
    output logic                bvalid,
    input  logic                bready
);
    logic [ADDR_W-1:0] addr_q;
    logic              aw_done, w_done;
 
    // AW: assert READY independently of VALID (accept whenever idle).
    // READY may depend on VALID; VALID must never depend on READY.
    always_ff @(posedge aclk or negedge aresetn)
        if (!aresetn)           awready <= 1'b0;
        else                    awready <= !aw_done;     // ready until captured
 
    always_ff @(posedge aclk or negedge aresetn)
        if (!aresetn)         { aw_done, addr_q } <= '0;
        else if (awvalid && awready) begin
            addr_q  <= awaddr;                            // capture on handshake
            aw_done <= 1'b1;
        end else if (bvalid && bready) aw_done <= 1'b0;   // clear when txn closes
 
    // W: accept the data beat.
    always_ff @(posedge aclk or negedge aresetn)
        if (!aresetn)        wready <= 1'b0;
        else                 wready <= !w_done;
 
    always_ff @(posedge aclk or negedge aresetn)
        if (!aresetn)        w_done <= 1'b0;
        else if (wvalid && wready && wlast) w_done <= 1'b1;
        else if (bvalid && bready)          w_done <= 1'b0;
 
    // B: respond only AFTER the write data is accepted (B-after-W rule).
    always_ff @(posedge aclk or negedge aresetn)
        if (!aresetn) begin bvalid <= 1'b0; bresp <= 2'b00; end
        else if (aw_done && w_done && !bvalid) begin
            bvalid <= 1'b1;
            bresp  <= 2'b00;                              // OKAY
        end else if (bvalid && bready) bvalid <= 1'b0;    // response accepted
endmodule

The slave asserts awready/wready independently of the master's VALID (never the other way), and gates bvalid behind aw_done && w_done so the response can never precede the data.

8. Back-Pressure — A Slow Slave Stalls One Channel, Not the Bus

When the slave can't accept data immediately, it holds wready low; the master holds wvalid and wdata stable until the slave is ready. Because the channels are independent, this stalls only the W channel — AW for the next transaction can still make progress.

9. Industry Usage

• DRAM controllers: every AXI-attached DDR controller (mobile SoCs, server memory subsystems) ingests writes on AW/W and returns B per transaction; out-of-order BID lets it reorder for bank efficiency.
• NVMe / PCIe bridges: PCIe-to-AXI bridges in SSD controllers map memory writes onto AXI AW/W, and a DECERR here is how an unmapped BAR access surfaces.
• GPU / accelerator fabrics: Apple's and AMD's on-chip interconnects use AXI (and AXI-derived) write channels with deep outstanding-write windows to keep high-bandwidth engines fed.
• Register blocks: AXI4-Lite (a single-beat subset of exactly this handshake) is the near-universal control-register interface for IP blocks.

10. Debug Lab — Real AXI Write Bugs

// ❌ master: VALID depends on READY — illegal
always_ff @(posedge aclk)
    awvalid <= awready;   // never rises, because slave waits for awvalid

// ✅ assert awvalid when the address is available; hold until handshake
always_ff @(posedge aclk)
    if (have_addr && !(awvalid && awready)) awvalid <= 1'b1;
    else if (awvalid && awready)            awvalid <= 1'b0;

11. Q & A

12. Summary

An AXI4 write is three independent channels — AW (address) and W (data) master→slave, B (response) slave→master — each running the same VALID/READY handshake: the source asserts VALID from its own data-ready state, the destination asserts READY when it can accept, and the beat transfers on the ACLK edge where both are high, with VALID and its payload held stable until then. The channels decouple in time for throughput, bound by a small set of dependency rules: VALID never waits for READY (the deadlock guard), AW and W have no required order in AXI4, and B must follow the write data — never precede it.

The B response carries BRESP: OKAY/EXOKAY for success, SLVERR (the slave rejected a valid address) and DECERR (no slave at that address) for failure — and a master that ignores BRESP is a real bug class. The three bugs that dominate AXI bring-up are the VALID-waits-for-READY deadlock, bvalid before the W handshake, and a master that never asserts bready — and each has a distinct, recognisable signature on a bus capture. Master the write handshake here and the read channel (AR/R), bursts, and out-of-order IDs are the same handshake with more payload.

Next: AXI4 Read Channel — AR & R — the read trio and last-beat behaviour. Bursts (AxLEN/AxSIZE/AxBURST), out-of-order AxID, and WSTRB narrow transfers build on this handshake in the following lessons.